While many open-source enthusiasts like to flaunt RISC-V as not having the security challenges as x86_64 CPUs have seen over the past several years with various speculative execution / side-channel attacks and arguing for the benefits of an open-source ISA in stronger security, in practice it’s not so clear-cut. Security researchers at Germany’s CISPA Helmholtz Center for Information Security have found current RISC-V CPU implementations coming up short for their actual security.

Fabian Thomas and Lukas Gerlach of CISPA presented at FOSDEM 2026 this weekend in Brussels on RISC-V CPU security. They have been evaluating the security of RISC_V processor implementations in relation to the transient execution attacks and security problems that have given x86_64 CPUs much frustration in recent years. Unfortunately, the RISC-V situation isn’t nearly as ideal and even with being a younger and cleaner ISA, there are vulnerabilities. There’s also the matter of Linux kernel Spectre patches for RISC-V lagging behind and only working their way to mainline now, even though they are vulnerable too and years after Arm and x86 processors saw their Spectre mitigations land.

Here’s the key takeaways from their FOSDEM talk abstract:

"This talk takes a critical look at how RISC-V implementations handle microarchitectural security today. We show that even "simple" in-order designs already suffer from architectural flaws and powerful side channels. In our earlier work, we demonstrated novel attacks, such as Cache+Time and CycleDrift, on the first commercial RISC-V CPUs, exploiting unprivileged access to instruction-retirement counters and cache-timing leakage.

But manual analysis does not scale. RISCover, our open-source differential fuzzing framework, automatically discovers architectural vulnerabilities across closed-source RISC-V CPUs. By comparing instruction behavior across 8 commercial CPUs from 3 vendors, RISCover found what manual analysis missed: GhostWrite, a bug in T-Head’s XuanTie C910 that lets unprivileged code write directly to physical memory, completely bypassing virtual memory isolation. We also discovered multiple "halt-and-catch-fire" sequences that crash CPUs from userspace, leading to denial-of-service.

These findings reveal a pattern: while the RISC-V specification provides strong security primitives (e.g., PMP and cleaner privilege separation), implementations consistently choose insecure defaults—leaving unprivileged timing sources enabled, shipping undocumented vendor extensions like XTheadVec without proper validation, and omitting features to limit speculation. RISC-V is at an inflection point: the architecture is still young enough to fix, but adoption is accelerating fast. The decisions vendors make today—insecure defaults, unvalidated extensions, missing mitigations—will be baked into billions of chips we cannot patch."

If RISC-V CPU security interests you, the video recording and slide deck from this FOSDEM 2026 presentation can be found at FOSDEM.org.