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🔧 Hardware
Broad
CPU Architecture, Microarchitecture, Silicon
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202094
posts in
36.4
ms
Show HN: I built a small
repertoir
of different
computing
systems
🖥️
Hardware Architecture
computers.tugdual.fr
·
1d
·
Hacker News
HyDRA
: Deadline and Reuse-Aware
Cacheability
for Hardware Accelerators
🖥️
Hardware Architecture
arxiv.org
·
3d
Dedicated
Servers
⚙️
CPUs
nocix.net
·
2h
matthewworner/spike
: Spike is a weight block
pager
for large language models.
🏗️
LLM Infrastructure
github.com
·
7h
·
Hacker News
AMD launches Ryzen 9 Pro 9965X3D and Ryzen 7 Pro
9755X3D
, the world's first Pro-series Ryzen chips with
3D-VCache
⚙️
CPUs
tweaktown.com
·
1d
Custom
PC
Builder
- Build Your Own PC
⚙️
CPUs
newegg.ca
·
3d
·
r/computers
Scaling PCIe Controllers for AI
Bandwidth
: A
Multistream
Architecture Analysis for 64 GT/s and 128 GT/s
🎮
GPU Microarchitecture
semiengineering.com
·
1d
The case for
fine-grained
tracking of
compute
for AI
📊
AI Performance Profiling
lesswrong.com
·
1d
RVA23-compliant
K3 Pico-ITX SBC and
K3-CoM260
SoM feature SpacemiT K3 octa-core RISC-V AI SoC, up to 32GB RAM, 256GB UFS
🔌
Embedded Systems
cnx-software.com
·
3d
Show HN: How
Scaleway
brought the first
RISC-V
servers to the cloud
🔌
Embedded Systems
scaleway.com
·
2d
·
Hacker News
Getting peak TOPS on a
Ryzen
AI 7 350
NPU
🖥️
Hardware Architecture
destevez.net
·
6d
·
Lobsters
,
Hacker News
nviennot/core-to-core-latency
: Measures the latency between CPU
cores
⚙️
CPUs
github.com
·
2d
·
Hacker News
Hardware
Memory Models (Memory Models, Part 1)
🖥️
Hardware Architecture
research.swtch.com
·
6d
·
Hacker News
Enhancing Instruction
Prefetching
via Cache and
TLB
Management
🖥️
Hardware Architecture
arxiv.org
·
2d
AMD's
X970E
chipset rumored to reuse the
PROM21
chipset, but with native support for CUDIMM
🎮
Console Hardware
tweaktown.com
·
6d
A
Reconfigurable
Multiplier
Architecture for Error-Resilient Applications in RISC-V Core
🖥️
Hardware Architecture
arxiv.org
·
3d
EDA-Schema-V2
: A Multimodal
Schema
, Open Datasets, and Benchmarks for Machine Learning in Digital Physical Design
🏗️
Computational Architecture
arxiv.org
·
4d
EULER-ADAS: Energy-Efficient & SIMD-Unified
Logarithmic-Posit
Engine for Precision-Reconfigurable Approximate ADAS Acceleration
🖥️
Hardware Architecture
arxiv.org
·
4d
TransDot
: An Area-efficient
Reconfigurable
Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines
🎯
Emulation Accuracy
arxiv.org
·
4d
Closer in the Gap: Towards Portable Performance on
RISC-V
Vector
Processors
🖥️
Modern CPU
arxiv.org
·
3d
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