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🖥️ Modern CPU
AVX-512, Vector Extensions, Branch Prediction, Cache Optimization
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202073
posts in
35.4
ms
Enhancing Instruction
Prefetching
via Cache and
TLB
Management
🖥️
Hardware Architecture
arxiv.org
·
2d
Getting peak TOPS on a
Ryzen
AI 7 350
NPU
🖥️
Hardware Architecture
destevez.net
·
6d
·
Lobsters
,
Hacker News
CPU-Z
download
v2.20
⚙️
CPUs
guru3d.com
·
19h
I
blamed
my budget CPU for poor performance until I
checked
these 4 things instead
💻
PC Gaming
xda-developers.com
·
12h
Show HN: I built a small
repertoir
of different
computing
systems
🖥️
Hardware Architecture
computers.tugdual.fr
·
1d
·
Hacker News
The Case For
Compilers
: A Look at SPEC CPU 2026 on
LLVM
22
💻
CPU Microarchitecture
servethehome.com
·
4d
Ryzen Pro 9000 Expansion Brings AMD's 3D V-Cache to
Mainstream
Workstations
⚙️
CPUs
hothardware.com
·
21h
AMD launches Ryzen 9 Pro 9965X3D and Ryzen 7 Pro
9755X3D
, the world's first Pro-series Ryzen chips with
3D-VCache
⚙️
CPUs
tweaktown.com
·
1d
matthewworner/spike
: Spike is a weight block
pager
for large language models.
🏗️
LLM Infrastructure
github.com
·
7h
·
Hacker News
A simple way to
compress
model, KV cache, flops
vias
low-rank with zero overhead
⚡
LLM Optimization
jeffreywong20.github.io
·
1d
·
Hacker News
AMD is making your OS better at
finding
the most powerful
CPU
core
⚙️
CPUs
club386.com
·
3d
nviennot/core-to-core-latency
: Measures the latency between CPU
cores
⚙️
CPUs
github.com
·
2d
·
Hacker News
Running local models on an
M4
with 24GB memory
🏠
Local LLM Deployment
news.ycombinator.com
·
3d
·
Hacker News
What Actually
Happens
Inside a
CPU
When Code Runs
💻
CPU Microarchitecture
siliconopera.com
·
4d
Can memory-hard PoW still
meaningfully
reduce
ASIC/GPU
advantage?
🧩
Memory Disambiguation
pastebin.support.one
·
5d
·
Hacker News
AMD Ryzen 7 PRO 9755
Surfaces
With
Slight
Multi-Core Performance Gain
⚙️
CPUs
guru3d.com
·
6d
Closer in the Gap: Towards Portable Performance on
RISC-V
Vector
Processors
💻
CPU Microarchitecture
arxiv.org
·
3d
KV-RM
:
Regularizing
KV-Cache Movement for Static-Graph LLM Serving
🎯
Data Locality
arxiv.org
·
3d
HyDRA
: Deadline and Reuse-Aware
Cacheability
for Hardware Accelerators
🖥️
Hardware Architecture
arxiv.org
·
3d
AccelSync
:
Verifying
Synchronization Coverage in Accelerator Pipeline Programs
🎯
Emulation Accuracy
arxiv.org
·
4d
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