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HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators  🖥️Hardware Architecture
arxiv.org·2d
Scalable Shopify Integration Patterns Every Developer Should Know  🏛️Technical Architecture
kolachitech.com·5h·DEV
Cache Stampede Prevention in Go — 1k req/s load test + full monitoring stack  ⚡Redis
github.com·3d·r/golang
Scaling PCIe Controllers for AI Bandwidth: A Multistream Architecture Analysis for 64 GT/s and 128 GT/s  🎮GPU Microarchitecture
semiengineering.com·1d
Architecting on Cloudflare  🏛️Technical Architecture
architectingoncloudflare.com·5d·Hacker News
The case for fine-grained tracking of compute for AI  📊AI Performance Profiling
lesswrong.com·1d
KVServe: Service-Aware KV Cache Compression for Communication-Efficient Disaggregated LLM Serving  🌊Streaming Compression
arxiv.org·23h
MLCommons Chakra: Advancing Performance Benchmarking and Co-design using Standardized Execution Traces  ⚡Performance Mythology
arxiv.org·1d
DICE: Enabling Efficient General-Purpose SIMT Execution with Statically Scheduled Coarse-Grained Reconfigurable Arrays  🎮SIMT Execution
arxiv.org·6d
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton  ⚡High Performance Computing
arxiv.org·2d
Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors  🖥️Modern CPU
arxiv.org·2d
ScarfBench: A Benchmark for Cross-Framework Application Migration in Enterprise Java  🔌Interface Evolution
arxiv.org·3d
Enhancing Instruction Prefetching via Cache and TLB Management  🖥️Hardware Architecture
arxiv.org·1d
Rethinking Adapter Placement: A Dominant Adaptation Module Perspective  📊AI Performance Profiling
arxiv.org·6d
FractalSortCPU: Bandwidth-Efficient Compressed Radix Sort on CPU  📊Columnar Databases
arxiv.org·2d·Hacker News
TopoU-Net: a U-Net architecture for topological domains  🌐Archive Topology
arxiv.org·2d
From Map-and-Encap to BIER: Observations on Network Routing Scalability  🕸️Network Topology
arxiv.org·3d
SHIA: A Direct SysML-Hardware Interface Architecture for Model-Centric Verification  🔌MCP Protocol
arxiv.org·1d
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments  🎮GPU Microarchitecture
arxiv.org·2d·Hacker News
Harness Engineering as Categorical Architecture  🤖AI Engineering
arxiv.org·1d

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