💾 Caches - Jullang

⚙️Systems Programming News Blog Discussion

irexta.com··DEV

AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum Cache

⏩SIMD

techpowerup.com··r/hardware

Intelligent inference scheduling with llm-d on Red Hat AI

🤖AI

developers.redhat.com·

New comment by Nya-kundi in "Ask HN: Who wants to be hired? (June 2026)"

⚡Cache Optimization

emmanuel326.github.io··Hacker News

I wrote a simple multithreaded code in Rust, but the performance didn’t increase much with an…

⚡Cache Optimization Blog

medium.com

Simplifying Weak Reference Processing in ZGC

🧹Memory Management

inside.java·

jianzhichun/permafrost: Freeze Claude Code's prompt prefix so DeepSeek's automatic cache always hits — alignment proxy + coalescing + keepalive, installable as a CC plugin. Measured 64% cheaper on real Claude Code traffic.

⏱️Tokio Code

github.com··Hacker News

PZSDR P047 RF-ADC and RF-DAC high-end SDR board is based on AMD Zynq UltraScale+ ZU47DR RFSoC (Crowdfunding) - CNX Software

🖥️RISC-V News

cnx-software.com·

The Return of Rigorous Full-System Timing Simulation

⚡Cache Optimization

sigarch.org··Hacker News

Graviton5’s improved design increases speed and energy efficiency — beyond Moore’s law

🎲Property Testing Blog

amazon.science··Hacker News

AMD Zen 6 Leak: Next-Gen Ryzen Processors Tipped To Clear 6.5GHz Barrier

🖥️RISC-V News

hothardware.com·

G.Skill explains how AMD EXPO ULL unlocks additional performance — expanded profiles allow memory makers to include subtiming tweaks for the first time

⚡Cache Optimization News

tomshardware.com

dod hash-trie - gardenweb

⚡Cache Optimization

napcakes.nekoweb.org··r/C_Programming

Raspberry Pi 5 – 16 GB, $350

🖥️RISC-V

adafruit.com··Hacker News

Massive AI Storage Demand Creates a New Memory Wall

🏞️Region-based Memory News

eetimes.com·

AWS Graviton5 available via M9g and M9gd instances

🎲Property Testing

techzine.eu·

Evaluating flood risk management performance under climate change based on nature-based solutions — empirical evidence from Taihu Lake Basin

🔢Linear Types Academic

sciencedirect.com·

Zero-Click HFP/A2DP Takeover via L2CAP Session Preemption

Why Your CPU Is Fast but Your Program Is Slow: Understanding the Memory Wall

Toward Intelligent Prefetching: A Survey on Complex Memory Access Prediction Techniques

AMD EPYC 8005 Bare Metal Server Review: The Engineering Truth

AMD Ryzen 9 9950X3D2 Dual Edition Review - Maximum Cache

Intelligent inference scheduling with llm-d on Red Hat AI

New comment by Nya-kundi in "Ask HN: Who wants to be hired? (June 2026)"

I wrote a simple multithreaded code in Rust, but the performance didn’t increase much with an…

Simplifying Weak Reference Processing in ZGC

jianzhichun/permafrost: Freeze Claude Code's prompt prefix so DeepSeek's automatic cache always hits — alignment proxy + coalescing + keepalive, installable as a CC plugin. Measured 64% cheaper on real Claude Code traffic.

PZSDR P047 RF-ADC and RF-DAC high-end SDR board is based on AMD Zynq UltraScale+ ZU47DR RFSoC (Crowdfunding) - CNX Software

The Return of Rigorous Full-System Timing Simulation

Graviton5’s improved design increases speed and energy efficiency — beyond Moore’s law

AMD Zen 6 Leak: Next-Gen Ryzen Processors Tipped To Clear 6.5GHz Barrier

G.Skill explains how AMD EXPO ULL unlocks additional performance — expanded profiles allow memory makers to include subtiming tweaks for the first time

dod hash-trie - gardenweb

Raspberry Pi 5 – 16 GB, $350

Massive AI Storage Demand Creates a New Memory Wall

AWS Graviton5 available via M9g and M9gd instances

Evaluating flood risk management performance under climate change based on nature-based solutions — empirical evidence from Taihu Lake Basin