Be Careful When Assigning ArenaAllocators (2024)
openmymind.net·17h·
Discuss: Lobsters, Hacker News
🏗️Custom Allocators
Conquering the LLM Memory Wall: How to Run 2–4x Longer Contexts with a Single Line of Code
reddit.com·1d·
Discuss: r/LocalLLaMA
🗺️Region Inference
What happens when you run a program?
dev.to·1d·
Discuss: DEV
📜Bytecode Interpreters
Model Kombat by HackerRank
producthunt.com·13h
🏁Language Benchmarks
Machine Scheduler in LLVM
myhsu.xyz·10h·
Discuss: Hacker News
📅Instruction Scheduling
The three game-changing features of JDK 25
infoworld.com·8h
⚡Interpreter Optimization
VulAgent: Hypothesis-Validation based Multi-Agent Vulnerability Detection
arxiv.org·13h
🔍Static Analysis
Cost-Effective, Orthogonal Approach to Resilient Memory Design (Univ. of Central Florida, UT San Antonio, Rochester)
semiengineering.com·10h
🧠Memory Models
A (Nearly) Branchless RESP Request Parser
kevinmontrose.com·1d
🔧Error Recovery
Necessary tool? Async LoRA for distributed systems
news.ycombinator.com·13h·
Discuss: Hacker News
📡Erlang BEAM
Network Storage and Scaling Characteristics of a Distributed Filesystem
maknee.github.io·2h·
Discuss: Hacker News
⚡Performance
Learning Rust and a bit unclear about an exercise on Exercism
exercism.org·5h·
Discuss: r/rust
🦀Rust Macros
From $0 to $40M ARR: Inside the tech that powers Bolt.new
newsletter.posthog.com·46m·
Discuss: Hacker News
🚀V8 Internals
Zettelkasten for Programmers: Processing Swift Actor Usage Advice in Depth
christiantietze.de·11h
✨Gleam
Safepoints and Fil-C
fil-c.org·13h·
Discuss: Hacker News
🎯Ring Buffers
LLMs on a Shoestring: The Dynamic Cache Advantage by Arvind Sundararajan
dev.to·1d·
Discuss: DEV
💾Cache Algorithms
Be Engineering Insights: Adventures in Graphics Drivers
haiku-os.org·4h·
Discuss: Hacker News
💾Register Pressure
Optimizing Code Cache Performance for Large Code Footprint Java Applications on Neoverse
community.arm.com·11h
⚡Cache Optimization
Autoscaling Insights: What Nearly A Decade Of Autoscaling Your Apps Has Revealed To Us
judoscale.com·1d
📮Message Queues
Rowhammer: TRR on DDR5 DRAM has been broken
comsec.ethz.ch·1d·
Discuss: Hacker News, r/hardware
🏷️Memory Tagging