⏲️ Embedded GC - abnv · Scour

Streamlining CUB with a Single-Call API

developer.nvidia.com·2h

🏗️Custom Allocators

Computer-on-Modules for an efficient entry into rugged embedded edge AI applications

einpresswire.com·1d

🔌Microcontrollers

Reduction for Structured Concurrent Programs

arxiv.org·18h

🔀Concurrency Models

GNU C Language Manual

gnu.org·4h

🪄C Metaprogramming

ANN v3: 200ms p99 query latency over 100 billion vectors

turbopuffer.com·23h·

Discuss: Hacker News

⚡Cache-Aware Algorithms

Real-Time Data Stream Processing in Go: Backpressure, Windowing, and Fault Tolerance Explained

dev.to·9h·

Discuss: DEV

📡Async Channels

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🤝Cooperative Threading

Addressing Critical Tradeoffs In NPU Design

semiengineering.com·15h

🏰Capability Machines

DCAC: Dynamic Class-Aware Cache Creates Stronger Out-of-Distribution Detectors

arxiv.org·18h

⚡Cache-Aware Algorithms

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·11h

🗺️Region Inference

Making an LSP for great good

thunderseethe.dev·23h·

Discuss: Lobsters, Hacker News

understanding LSM trees via read, write, and space amplification

bitsxpages.com·29m

🔗Memory Linearization

Rust async combinators for elegant and secure concurrency

kerkour.com·17h·

Discuss: r/rust

🪆Embedded DSLs

Setting Up A Cluster of Tiny PCs For Parallel Computing - A Note To Myself

kenkoonwong.com·4h·

Discuss: Hacker News

🔀SIMD Programming

One ISA, Infinite Use Cases: RISC-V and the Road to Workload-Specific Silicon

riscv.org·3h

Memory Addressing and Memory Mapped I/O | by Tom Herbert | Jan, 2026

medium.com·2d

💾Allocator Design

FastMCP 3.0: From Tool Servers to Context Applications

mcpstatus.io·1d·

Discuss: Hacker News

🌉Cross-Platform FFI

Open-Source FPGA Implementation of an I3C Controller[v1]

preprints.org·1d

⚡Control Synthesis

Analog hardware may solve Internet of Things' speed bumps and bottlenecks

techxplore.com·2h

🔌Microcontrollers

Scalable Adaptive Memory Compiler Optimization via Multi-Objective Evolutionary Algorithms

dev.to·21h·

Discuss: DEV

🧠Memory Hierarchy

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