🔧 RISC-V - anoop · Scour

RISC-V Summit Europe 2026 🔬RISC-V Security

riscv-europe.org·5d·r/linux

CPU IP processes mixed scalar and vector workloads 💾CPU Architecture

RISC-V and Floating Point 🔬RISC-V Security

fprox.substack.com·2d·Substack

NASA builds space-grade AI compute 🔧System Design

jonpeddie.com·7h

Firefly CSC2-N48SPK3 – A 2880 TOPS RISC-V AI server with 48 SpacemiT K3 Nodes, 48 NVMe SSDs 💾CPU Architecture

cnx-software.com·1d

HWE Bench: A new unbounded Benchmark for LLMs (GPT 5.5 is on top) ⚙️Compilers

hwebench.com·5d·Hacker News

Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX 💾CPU Architecture

phoronix.com·13h·Hacker News

The RISC-V Code Models (2026 Edition): medlow, medany, & large 🔬RISC-V Security

Difference between revisions of "ELC 2026 Presentations" ⚙️Computer Architecture

elinux.org·10h

karagure/rvkit: Rust + Zig CLI/TUI toolchain for RISC-V microcontroller development. Scaffold, build, flash, monitor. 🔬RISC-V Security

github.com·2d·r/Zig, r/embedded

simdutf: simdutf: Text processing at billions of characters per second ⚙️Compilers

simdutf.github.io·4d

When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform 🔧System Design

eetimes.com·18h

Practical Reverse Engineering ⚙️Assembly

datanoisetv.github.io·1d

SiFive Upgrades P500 RISC-V IP Cores 💾CPU Architecture

embedded.com·6d

Banana Pi BPi-RV2 RISC-V Router Board 🔬RISC-V Security

youtube.com·1d·r/SBCs

Nvidia: Latest news and insights 🔒Tailscale Blog

networkworld.com·10h

OpenBSD 7.9 boosts AMD64 CPU core support, adds delayed hibernation and improves scheduler 🔬RISC-V Security

alternativeto.net·15h

Canonical Launches Ubuntu Core 26 with Live Kernel Patching, Optimized Updates 💾CPU Architecture

9to5linux.com·1d

GenAI-Driven Approach to RISC-V Supply Chain Exploration 🖧Distributed Systems

Researchers break the 'memory wall' in large-scale AI training 🖧Distributed Systems

techxplore.com·2d

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