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🏗️ Computer Architecture
CPU Design, Pipelining, Cache, Memory Hierarchy
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The 1:1 Myth: Why Your CPU Can Handle 400
Threads
on 4
Cores
dev.to
·
1d
·
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DEV
🔧
hardware
AI
Infra
HPC
dev.to
·
1d
·
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DEV
🔧
hardware
Performance
Antipatterns
: Angel or
Devil
for Power Consumption?
arxiv.org
·
1d
🔧
hardware
AI in Multiple
GPUs
: Point-to-Point and
Collective
Operations
towardsdatascience.com
·
1d
🔧
hardware
Introduction
faiface.github.io
·
2h
🔧
hardware
PAM: Processing Across Memory
Hierarchy
for Efficient
KV-centric
LLM Serving System
arxiv.org
·
1d
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hardware
How low-bit
inference
enables
efficient AI
dropbox.tech
·
7h
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Hacker News
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hardware
chrisarg/Bit
: A Bit
vector
library for learning fun and also work
github.com
·
2h
🔧
hardware
I
struggled
with system design until I learned these 114
concepts
newsletter.systemdesign.one
·
2h
🔧
hardware
Best CPU 2026 – the top AMD
Ryzen
and Intel Core
processors
tested
club386.com
·
1d
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hardware
Oxide
plans new rack attack,
packing
in Zen 5 CPUs and DDR5 RAM
theregister.com
·
21h
·
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Hacker News
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Discussion - Investigation of Single Thread CPU "
Thoughput/cycle
"
forums.anandtech.com
·
2d
🔧
hardware
Intel Posts 2026 Update For
Cache
Aware
Scheduling
On Linux
phoronix.com
·
1d
🔧
hardware
Breaking the
Tractability
Barrier: A Generic Low-Level Solver for
NP-Hard
Instances (N=63) on Commodity 64-Bit Silicon
zenodo.org
·
1d
·
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Instruction
decoding in the Intel 8087
floating-point
chip
righto.com
·
1h
·
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Hacker News
,
Blogger
🔧
hardware
Table of
Contents
- Data Engineering for Large Models: Architecture,
Algorithms
& Projects
datascale-ai.github.io
·
14h
·
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Lobsters
🔧
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I updated the
README
and my Benchmarks
Regressed
codspeed.io
·
3h
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hardware
As
Complexity
Grows, Architecture
Dominates
Material
worksonmymachine.ai
·
3h
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🔧
hardware
Chained
Assignment in Python
Bytecode
loriculus.org
·
10h
·
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Hacker News
🔧
hardware
CUDA
Shared Memory Bank Conflict-Free
Vectorized
Access
leimao.github.io
·
1d
🔧
hardware
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