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🏗️ Computer Architecture
CPU Design, Pipelining, Cache, Memory Hierarchy
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121717
posts in
2.19
s
DeltaKV
:
Residual-Based
KV Cache Compression via Long-Range Similarity
arxiv.org
·
2d
🔧
hardware
CPUs
are Back: The
Datacenter
CPU Landscape in 2026
newsletter.semianalysis.com
·
2d
·
Discuss:
r/hardware
🔧
hardware
百度千帆推出
AI
编码订阅服务
Coding Plan
linux.do
·
6h
👨
hacking
AFMTJ
Model For In-Memory Computing (University of
Arizona
)
semiengineering.com
·
1d
🔧
hardware
[Paper] How does information access affect LLM
monitors
' ability to detect
sabotage
?
lesswrong.com
·
10h
👨
hacking
Code
Coherence
: The Performance
Metric
No One Measures
dev.to
·
5h
·
Discuss:
DEV
🔧
hardware
Architecture
of
SQLite
sqlite.org
·
19h
·
Discuss:
Hacker News
🔧
hardware
Introducing
Dedicated
Container Inference:
Delivering
2.6x faster inference for custom AI models
together.ai
·
7h
🔧
hardware
Quick
Stack
Tiedown
artlu.bearblog.dev
·
12h
🔧
hardware
laphilosophia/strime
: Streaming projection engine — extract fields at multi-gigabit speeds with O(1) memory
github.com
·
16h
·
Discuss:
r/node
🔧
hardware
Samsung: "Expanding CPU Capabilities for On-device AI with Arm
SME2
[as implemented in the
Exynos
2600]"
semiconductor.samsung.com
·
1d
·
Discuss:
r/hardware
🔧
hardware
Everything I know about good system design
seangoedecke.com
·
2d
🔧
hardware
Distributed Hybrid
Parallelism
for Large Language Models:
Comparative
Study and System Design Guide
arxiv.org
·
1d
🔧
hardware
RCBldEng
- a computationally efficient RC network modeling method and engine for
multizone
building simulation
sciencedirect.com
·
17h
🔧
hardware
High-Level Rust: Getting 80% of the
Benefits
with 20% of the
Pain
hamy.xyz
·
1d
🔧
hardware
Intel "Nova Lake" Compute
Tile
Die-sizes
Surface
techpowerup.com
·
19h
🔧
hardware
Cisco: New 102.4
Tbit/s
Switching Chip Silicon One
G300
for AI Data Centers
europedigital.cloud
·
16h
🔧
hardware
Avoiding
UB
but "safe" data race in a lock-free slab
allocator
- help - The Rust Programming Language Forum
users.rust-lang.org
·
12h
🔧
hardware
G.Skill reaches $2.4 million
DDR4
and DDR5 memory speed settlement, changes to OC speed
labels
proposed
videocardz.com
·
21h
🔧
hardware
Duplex
Wirespeed
Packet Capture and Extraction Solution for
400G/200G
Networks
gl.com
·
15h
🔧
hardware
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