⚡ RISC-V - beachlorn · Scour

Talk about Open Source Chip Development with RISC-V 💾CPU Architecture

youtube.com·6d·Hacker News

RISC-V 101 – what is it and what does it mean for Canonical? 💾CPU Architecture

ubuntu.com·2d·Hacker News

QRV, a QNX-derived 64-bit OS, boots on the real RISC-V hardware for the first time 💾CPU Architecture

r-tty.blogspot.com·17h·r/embedded

Q1’26 RISC-V Market Update from Jon Peddie Research 💾CPU Architecture

jonpeddie.com·3h

AlmaLinux Kitten Gets Its Claws Into RISC-V 💾CPU Architecture

linuxtoday.com·2d

789 KB Linux Without MMU on RISC-V (2023) 💾CPU Architecture

popovicu.com·19h·Hacker News

Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance 💾CPU Architecture

mummanajagadeesh.github.io·3d·Lobsters, Hacker News

RISC-V chip design startup SiFive nabs $400M investment 💾Embedded Systems

siliconangle.com·23h

RISC-V 101 – what is it and what does it mean for Canonical? 💾CPU Architecture

lemmy.ml·2d

RISC-V SoC supports voice-enabled IoT devices 💾CPU Architecture

edn.com·1d

RISC-V Has Momentum. The Real Question Is Who Can Deliver 💾CPU Architecture

semiwiki.com·4d

John Mashey on 64-bit computing (1991) 💾CPU Architecture

bourguet.org·1d·Lobsters, Hacker News

Show HN: Anos – a hand-written ~100KiB microkernel for x86-64 and RISC-V ⚙️Systems Programming

github.com·6d·Hacker News

Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design ⚙️Program Synthesis

arxiv.org·2d

My Login Shell in Assembly 🔩Assembly

isene.org·2d·Lobsters, Hacker News

SPLASH: SPeculative Leakage-Adaptive Secure Hardware ⚡Concurrency

eprint.iacr.org·3d

High-Performance RK3568 SOM Module for Industrial and AI App 💾Embedded Systems

hackster.io·1d

RISC-V Optimized strnlen Implementation For Linux 7.1 Yields Big Speed-Up 💾CPU Architecture

phoronix.com·1d

*BSD discovery on the PINE64 ROCKPro64 🐧Linux

tumfatig.net·3d

Algorithms for Modern Hardware ⚡Concurrency

en.algorithmica.org·1d·Hacker News

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