⚙ Risc-v - bitfield · Scour

RISC-V Summit Europe 2026 📜Bytecode

riscv-europe.org·5d·r/linux

RISC-V and Floating Point 🔧Assembly Language

fprox.substack.com·2d·Substack

CPU IP processes mixed scalar and vector workloads 🔧Assembly Language

NASA builds space-grade AI compute 🛰️Space Technology

jonpeddie.com·7h

The RISC-V Code Models (2026 Edition): medlow, medany, & large 🔧Assembly Language

SiFive Upgrades P500 RISC-V IP Cores 📜Bytecode

embedded.com·6d

Initial Benchmarks Of The SpacemiT K3 RVA23 RISC-V CPU With The K3 Pico-ITX 🔧Assembly Language

phoronix.com·13h·Hacker News

karagure/rvkit: Rust + Zig CLI/TUI toolchain for RISC-V microcontroller development. Scaffold, build, flash, monitor. 🦀Rust programming language

github.com·2d·r/Zig, r/embedded

Difference between revisions of "ELC 2026 Presentations" 🚀Spacecraft Navigation

elinux.org·10h

Start9 RISC-V Router features SpacemiT K1 SoC, runs StartWRT OpenWrt fork (Crowdfunding) 🐹Golang

cnx-software.com·5d

Practical Reverse Engineering 💾Vintage Computing

datanoisetv.github.io·1d

Nvidia: Latest news and insights 🕰️Computing History

networkworld.com·10h

When Arm Meets RISC-V: SiPearl, Semidynamics to Co-Develop Sovereign AI Platform 🖥️Bytecode VMs

eetimes.com·18h

Intel and Qualcomm circle Tenstorrent as the NVIDIA-alternative trade comes due 🚀Space Exploration

thenextweb.com·1d

simdutf: simdutf: Text processing at billions of characters per second 📜Bytecode

simdutf.github.io·4d

Banana Pi BPi-RV2 RISC-V Router Board 💾Vintage Computing

youtube.com·23h·r/SBCs

#646, May 18th 2026 🦀Borrow Checker

llvmweekly.org·2d

GenAI-Driven Approach to RISC-V Supply Chain Exploration 🖥️Bytecode VMs

brucehoult/k3_ai: Utility to start a program on the A100 "AI" cores on SpacemiT K3 machines. 🔧Assembly Language

github.com·7h·Hacker News

Researchers break the 'memory wall' in large-scale AI training 🚀Space Robotics

techxplore.com·2d

Log in to enable infinite scrolling