🔓 RISC-V - dane8036

coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.

🔲System on chip Code

github.com··Hacker News

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software

🔲System on chip News

cnx-software.com·

SpacemiT shows off usably quick RISC-V mini desktop

🔲System on chip News

theregister.com··r/hardware

RISC-V edge box packs dual GbE, CAN, and 4G/5G support

🔲System on chip

linuxgizmos.com·

NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC

🔲System on chip

hpcwire.com··r/hardware

Milwaukee Striker: How Much Does The World's First Cordless Hammer Chisel Cost?

📱Edge AI

slashgear.com·

The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04

🔲System on chip Blog

blog.ludovic.dev··Hacker News, Hacker News

SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

🔲System on chip Academic

arxiv.org·

The Daily Heller: More English Textile Trademark Stamps

💎ASIC Design

printmag.com·

Reader’s Rig: Riley’s Specialized Chisel HT

🦵Running Form

bikepacking.com·

Less-relevant results

Difference between revisions of "ELC 2026 Presentations"

🔲System on chip

elinux.org·

The MilkV Jupiter 2/SpacemiT K3

🔲System on chip

taoofmac.com··Hacker News, Hacker News

Docker 29 and COPY –link –chown

🔲System on chip Blog

tunbury.org·

Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support

RISC-V Targets Data Centers, Edge AI, Space

Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds

Vortex expands open RISC-V graphics

Openchip taps Baya Systems data-movement platform for RISC-V systems

Open Source Hardware Certifications for May 2026

"RISC-V Is Now"

coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.

2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software

SpacemiT shows off usably quick RISC-V mini desktop

RISC-V edge box packs dual GbE, CAN, and 4G/5G support

NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC

Milwaukee Striker: How Much Does The World's First Cordless Hammer Chisel Cost?

The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04

SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC

The Daily Heller: More English Textile Trademark Stamps

Reader’s Rig: Riley’s Specialized Chisel HT

Difference between revisions of "ELC 2026 Presentations"

The MilkV Jupiter 2/SpacemiT K3

Docker 29 and COPY –link –chown