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CPU Architecture
🔬 CPU Architecture
Specific
microarchitecture, cache, pipeline, instruction set
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Intel 8086, the First
x86
chip, Enters its 50th Year in 2027
🖥️
Operating Systems
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
Breaking
architecture
barriers: Running
x86
games and apps on
ARM
(gpn24)
🐧
Linux
cdn.media.ccc.de
·
3d
3 days ago
Actions for Breaking architecture barriers: Running x86 games and apps on ARM (gpn24)
SpacemiT shows off usably quick
RISC-V
mini desktop
🐧
Linux
Content type:
News
theregister.com
·
9h
9 hours ago
Actions for SpacemiT shows off usably quick RISC-V mini desktop
The Tick-Tock AI Development Cycle.
🔧
Systems Programming
wilsoniumite.com
·
3h
3 hours ago
Actions for The Tick-Tock AI Development Cycle.
RISC-V
Summit Europe 2026: Industry and Academia
Unite
in Bologna to Advance Open Hardware
🚀
High Performance Computing
Content type:
News
eetimes.com
·
2d
2 days ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
⚙️
Compilers
Content type:
Academic
arxiv.org
·
20h
20 hours ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
RISC-V
And GPU Synergy In Practice: A Path Towards High-Performance SoCs
🐧
Linux
semiengineering.com
·
6d
6 days ago
Actions for RISC-V And GPU Synergy In Practice: A Path Towards High-Performance SoCs
Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
🐧
Linux
phoronix.com
·
1d
1 day ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
If a decade-old Nintendo Switch can run PC games, your next handheld doesn't need to be
x86
🐧
Linux
xda-developers.com
·
19h
19 hours ago
Actions for If a decade-old Nintendo Switch can run PC games, your next handheld doesn't need to be x86
Apple Chip
Architecture
from 1977 to 2026
🔧
Systems Programming
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
1d
1 day ago
Actions for Apple Chip Architecture from 1977 to 2026
Release v0.14.0-alpha.5 ·
UniClipboard/UniClipboard
🐧
Linux
Content type:
Code
github.com
·
4d
4 days ago
Actions for Release v0.14.0-alpha.5 · UniClipboard/UniClipboard
Intel introduced ‘the first processor in the
x86
series and the first 8086 microprocessor’ on this day in 1978 —
CPU
was designed as a temporary substitute for the delayed iAPX 432 project
🖥️
Operating Systems
Content type:
News
tomshardware.com
·
2d
2 days ago
Actions for Intel introduced ‘the first processor in the x86 series and the first 8086 microprocessor’ on this day in 1978 — CPU was designed as a temporary substitute for the delayed iAPX 432 project
Data center modernization unlocks AI budget headroom as enterprises fund new AI workloads
🚀
High Performance Computing
siliconangle.com
·
21h
21 hours ago
Actions for Data center modernization unlocks AI budget headroom as enterprises fund new AI workloads
"
RISC-V
Is Now"
🔧
Systems Programming
Content type:
Video
youtube.com
·
1d
1 day ago
·
Hacker News
Actions for "RISC-V Is Now"
Less-relevant results
OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel,
Arm
, and
RISC-V
hardware optimizations - CNX Software
⚡
Parallel Computing
Content type:
News
cnx-software.com
·
15h
15 hours ago
Actions for OpenCV 5 release - New DNN engine with enhanced ONNX and LLM/VLM support, Intel, Arm, and RISC-V hardware optimizations - CNX Software
OpenOCD User’s Guide
📡
Networking
Content type:
Reference
docs.jade.fyi
·
6d
6 days ago
Actions for OpenOCD User’s Guide
RISC-V
edge box packs dual GbE, CAN, and 4G/5G support
💾
Storage Systems
linuxgizmos.com
·
2d
2 days ago
Actions for RISC-V edge box packs dual GbE, CAN, and 4G/5G support
(
PR
) NextSilicon to Productize Arbel
RISC-V
Core Into 64-Core Enterprise Processor for AI and HPC
🚀
High Performance Computing
techpowerup.com
·
5h
5 hours ago
Actions for (PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
Why
x86
Zeroes a Register With `xor eax, eax`
🔧
Systems Programming
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
AMD Hits Record
X86
CPU
Market Share as Intel Supply Stalls in Q1
📈
Performance
hothardware.com
·
6d
6 days ago
Actions for AMD Hits Record X86 CPU Market Share as Intel Supply Stalls in Q1
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