💻 Chips - emschwartz · Scour

A deep dive into how ASML became a chokepoint for making cutting-edge chips by betting on EUV, close collaboration with TSMC and the US government, and more (Ne... 💎ASML

techmeme.com·3d

TSMC SoIC 3D stacking roadmap outlines path from 6-micron pitches today to 4.5-micron in 2029 — Fujitsu's Monaka CPU to benefit from face-to-face chiplet stacki... 🏭TSMC

tomshardware.com

·1d·Hacker News

Dr. Y.J. Mii on TSMC Technology Leadership in 2026 🏭TSMC

semiwiki.com·6h

NoC Coherency Challenges Balloon With AI SoCs And Chiplets 🔄Cache Coherence

semiengineering.com·16h

ASML Bibliography 💎ASML

neilhacker.com·2d·Hacker News

🍪 TWiC: TPU v8, Intel Rises Up, Marvell-Polariton 🖥GPUs

viksnewsletter.com·6d

The FPGA Milestone That Let Engineers Rewrite Chips Like Software 🖥️Hardware Architecture

spectrum.ieee.org

·2d·Hacker News

Intel bets the farm on AI inference to drag CPU back to the top table 🏗️LLM Infrastructure

theregister.com·6d

DeepSeek V4 Just Launched on Huawei Chips First 🖥GPUs

pub.towardsai.net

·5d

[AINews] DeepSeek V4 Pro (1.6T-A49B) and Flash (284B-A13B), Base and Instruct — runnable on Huawei Ascend chips 🖥GPUs

·5d

Intel soars on signs AI boom for CPUs is here 🖥GPUs

·6d·Hacker News

The Race to Make the World’s Most In-Demand Machine 🔗Technology Supply Chains

Dr. Cliff Hou and the TSMC N2 Process Technology 🏭TSMC

semiwiki.com·2d

Samsung, SK Hynix, and Micron earnings show increased DRAM prices, not shipments, indicating a focus on revenue over helping clients get the products they need ... 🖥GPUs

techmeme.com·9h

TSMC's details next-gen CoWoS roadmap: over 14-reticle packages and 48x leap in compute power expected by 2029 — massive size enables 24 HBM5E stacks and additional memory bandwidth jump 🏭TSMC

tomshardware.com

·3d·Hacker News

Shanghai-based Lightelligence, which makes photonics chips, surges by nearly 400% in its trading debut in Hong Kong after raising ~$310M in its IPO (Ann Cao/Sou... 🚀Startups

techmeme.com·2d

Chip Industry Week In Review 💎Semiconductor Trade

semiengineering.com·6d

Inside Google's TPU V8 strategy, delivering two chips for two crucial tasks — scale up size gives chips an advantage over Nvidia AI accelerators ⚡Hardware Acceleration

tomshardware.com

·3d

TSMC Tech Symposium 2026, By The Numbers 🏭TSMC

semiengineering.com·3d

The Shift to System-Level AI Drives Next-Generation Silicon 🏭TSMC

semiwiki.com·3d

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