🖥️ Hardware Architecture - emschwartz

🔓Hacking News

bleepingcomputer.com·

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures

⚡Systems Performance Academic

arxiv.org··Hacker News

hcarvalhoalves/lscpumac: A macOS shell script that displays CPU and system information in the same format as the Linux `lscpu` command.

🧠Memory Allocators Code

github.com··Hacker News

How much do amd64 microarchitecture levels help in Go?

⚡Systems Performance Blog

lemire.me··Lobsters, Hacker News, r/golang

Why x86 Zeroes a Register With `xor eax, eax`

⚡Systems Performance Blog

debasishg.github.io·

HVAC tech finds former AMD CEO Rory Read's PC in a customer's basement, signed by Lisa Su — unused 2014 desktop had Bulldozer-era hardware inside and a wrapped Windows 8.1 CD

🦎Oxide News

tomshardware.com

Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale

⚡Hardware Acceleration

ycombinator.com··Hacker News

Why AI code optimization needs production-grounded benchmarks

⚡Performance Blog

datadoghq.com··Hacker News

Gemini and Gopher Links 10/06/2026: Roasting, Changes, and Harms of Slop

📡RSS

techrights.org·

Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput

🏗️Search Infrastructure Blog

elastic.co·

Build settings in binary crates via cargo install and crates.io

📦Cargo

nnethercote.github.io··r/rust

Parallel SMT Solving via Dynamic Partitioning, Core-Guided Pruning, and Online Backbone Detection

🧮SMT Solvers Academic

arxiv.org·

Intel Macs replace PowerPC chips: Today in Apple history

🏛️Computer Architecture History

cultofmac.com·

rfgplk/micron.cpp: a pure C++ implementation (& redesign) of libc and the standard library

🌳Data Structures Code

github.com··Hacker News

Hacker News Trends: Search Hacker News super fast with Redis

🤖AI

hackernewstrends.com··Hacker News

Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was

⚡Fast AI Inference

theregister.com·

RISC-V And GPU Synergy In Practice: A Path Towards High-Performance SoCs

📱Edge AI Optimization

semiengineering.com·

MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs

📱Edge AI Optimization Academic

arxiv.org·

Apple Chip Architecture from 1977 to 2026

The Tick-Tock AI Development Cycle.

C0XMO botnet spreads via DD-WRT router flaw, kills rival malware

uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures

hcarvalhoalves/lscpumac: A macOS shell script that displays CPU and system information in the same format as the Linux `lscpu` command.

How much do amd64 microarchitecture levels help in Go?

Why x86 Zeroes a Register With `xor eax, eax`

HVAC tech finds former AMD CEO Rory Read's PC in a customer's basement, signed by Lisa Su — unused 2014 desktop had Bulldozer-era hardware inside and a wrapped Windows 8.1 CD

Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale

Why AI code optimization needs production-grounded benchmarks

Gemini and Gopher Links 10/06/2026: Roasting, Changes, and Harms of Slop

Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput

Build settings in binary crates via cargo install and crates.io

Parallel SMT Solving via Dynamic Partitioning, Core-Guided Pruning, and Online Backbone Detection

Intel Macs replace PowerPC chips: Today in Apple history

rfgplk/micron.cpp: a pure C++ implementation (& redesign) of libc and the standard library

Hacker News Trends: Search Hacker News super fast with Redis

Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was

RISC-V And GPU Synergy In Practice: A Path Towards High-Performance SoCs

MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs