Have you noticed how new smartphone models don’t seem to come out at as quick a clip as they did a decade ago? That’s partly due to the fact that you can’t pack more processing power into the same space without creating new thermal issues.

Pure transistor scaling has slowed down of late, but IBM and others are continuing to work toward smaller and smaller nodes. As transistor nodes get smaller, heat becomes a bigger problem. AI technologies, too, are driving increased chip power density and generating more heat.

Today IBM Research is announcing the results of its work under DARPA’s Thermonat, short for Thermal Design of Nanoscale Transistors, in which the IBM team modeled thermal behaviors of semiconductors all the way down to the atomic level.1 As part of IBM’s Thermonat effort, machine-learning software trained on IBM’s massive stores of semiconductor data achieved prediction accuracy within one degree, tens of thousands of times faster than the next best simulation tools.

For technologies like IBM’s advanced 2-nanometer node devices, where components are so thin that they’re just several atoms in thickness, the bulk equations found in the pages of physics textbooks can’t account for their heat properties.

“The entire industry is limited by heat right now,” said Russ Robison, a senior technical lead at IBM Research who worked on IBM’s Thermonat team. The more power that goes into a small area, the more likely engineers are to hit a wall where the heat produced by nanoscale transistors is difficult to dissipate. Through its participation in Thermonat, IBM aims to overcome this challenge.

The ability to accurately model heat sources in chips would provide a powerful tool to the engineers who are designing cooling systems for new chips, according to Timothy Chainer, a subsystem cooling and integration expert at IBM Research. “When designing chip layout, they can produce a thermally aware layout,” he said.

New technology requires new tools

Developing a model that can simulate the heating behavior of a given transistor required Robison and his colleagues to bring semiconductor engineering elements together with specialized software tools. They had to account for the thinness of transistors, their material properties at the atomic level, and the circuit-level tools used to measure them. They developed new machine learning code to build reduced-order models, simplified simulations of a system that maintain accuracy while reducing the number of data points to process.

What they ended up with was a minutely detailed understanding of exactly how the heat is generated in a chip, where it’s going, and which elements of circuit design will affect these properties. Their results exceeded DARPA’s requirements, which are famously difficult, said Robison. Whereas accuracy within 10% may be fine for an academic research project, DARPA needed the model to predict semiconductor heat properties within a 1% margin of accuracy. In the use cases the agency’s projects end up in, there is rarely room for error. Plus, it was looking for solutions to be 100 times faster than the state of the art — building a physical model of a new device to gather thermal data. Robison and his colleagues were able to model within 1°C of actual experimental data, or 0.002%, and they did it 50,000 times faster than current methods.

“It wasn’t thought that you could be this accurate, for as large of a circuit as we’re modeling,” Robison said. His team found that their method scales effectively to simulate circuits with millions of transistors. It can accurately model transient and steady state properties, including extremely accurate temperature readings at the transistor level.

Cross-pollination

Robison credits the pool of multidisciplinary talent within the walls of IBM Research for the team’s high accuracy. Materials scientists, experts who work with thermal systems, materials simulation experts, and others contributed their brainpower to the solution. IBM’s existing semiconductor technology was an invaluable resource, too: Robison and his colleagues exploited the vast trove of in-house data on IBM’s gate-all-around nanosheet technology to develop a model that can characterize transistor heat behavior.

“We had an incredible advantage,” Robison said. And now IBM has deep insight into the heating issues that can crop up as transistor nodes continue to get smaller and smaller. As the company moves forward to extend this research with partners, Robison likens the advances made under Thermonat to a bright set of headlights that will help illuminate the unknown behaviors of new technologies. “We have a tool that fully understands how the heat is generated in these devices and what we might need to do about it in the future.”

The result isn’t just accurate, it’s also fast, thanks to its reduced-order models of transistors. This was possible thanks to IBM’s trove of data, and the engineering simulation expertise of Ansys, with whom the team partnered on the project. A machine-learning technique called a Fourier neural operator, which employs a neural network training format, aided the development of these reduced-order models. The Fourier neural operator is particular to machine learning for solving partial differential equation matrices, so it was uniquely suited to this scenario, said Robison.

This tool could also help achieve more performance or efficiency out of chips, said Chainer. Improved cooling solutions would allow higher chip power at the same operating temperature to enable increased computational performance, Alternatively, more effective cooling solutions could achieve lower chip operating temperature which reduces chip power consumption to improve efficiency. The granularity of IBM’s modeling should be able to help with this. “When we design a cooling solution, we can optimize the chip power as well as removing the heat,” Chainer said.

While the result of IBM’s Thermonat effort is not a completely off-the-shelf tool, the workflow to develop it is repeatable, said Robison. The bulk of these new developments will remain in-house for use in IBM projects and those of IBM clients. In fact, it’s already being used by a team working on transistors at IBM, as well as another developing future three-dimensional integrated circuit (3D-IC) devices. And it’s versatile enough to be used for chip packaging and heterogeneous integration.

“We can apply this method to anywhere on a semiconductor where there could be a heating problem,” Robison said. “And we believe in those cases, too, it will be very fast, and very accurate.”