Over the last 12 months, it seems we have developed several FPGA-based boards, both as Adiuvo products and for clients. We have also been pulled into supporting FPGAs on boards that clients have designed. Often these client-designed boards have been developed on time-constrained schedules, and hence they are hoping for the best.

So I am going to start off the new year talking about how we are able to reduce the technical risk in our board designs.

The first thing to consider is how the board is going to be tested, ideally before the design and layout are completed. This allows us to think about the test access necessary for the board, what test points we want, and where we want them located. For example, we may want power and ground test points near power stages.

However, board bring-up goes beyond the simple identification of test points and requires that we can verify not only the manufacture and assembly, but also the functionality of components and devices before we drop on the application.

This is important because many of the projects I see that struggle follow the same pattern. They design the board, do a few simple power-on tests, and then drop on the application. You might get lucky reasonably often; however, when your application does not work, you are then in trouble.

The reason you are in trouble is that you have no idea where the issue lies. Is it within the application, for example one of the interfaces being implemented incorrectly in the FPGA? Or could it be a manufacturing issue, for example an incorrect component fitted or a wrongly fitted passive?

It is also going to take time to find the issue if all you have is the application, which is designed to provide functionality and not identify errors.

This is where, once the boards have been manufactured and tested, more complex test solutions can come into play. The best approach to this, especially if you have an FPGA on the board, is to leverage JTAG and boundary scan.

Boundary scan allows us to gain significant test coverage of the board, including checking BGA balls and the functionality of memories, oscillators, ADCs, and DACs. This ability enables us to ensure we are developing our application on a known good board, or to identify manufacturing and assembly issues without the need to adjust the application.

Like layers of an onion, each additional layer of testing enables us to find issues that might prevent the application from running. Finally, this leaves just the application itself to be debugged, at which point the engineers know that the issue more than likely lies within the application.

To take a look at boundary scan testing, I was recently loaned some XJTAG equipment and thought it would be a good idea to test, for demonstration purposes, one of the Spartan-7 tiles connected to the carrier card to provide JTAG access.

The Spartan-7 tile is pretty simple. It has a QSPI device for configuration memory, two user LEDs, and a small PSRAM.

Getting started was pretty simple. All I had to do was provide the ODB schematics and the bill of materials into the project.

Once the bill of materials and design are imported, we are able to assign components and devices to test programs.

For this simple example, I am initially going to just test the configuration memory and ensure it is functioning correctly.

Once the tests are planned, we are able to detect the JTAG chain using the BSDL files provided by AMD, which can be downloaded from their website.

We can then define the connection of the JTAG probe that we have connected to the Spartan-7 tile.

Once the scan chain is established, we are then able to run the tests. In this test, we are able to see that the configuration SPI is present on the board.

The SPI flash is present and can be detected and accessed. I am now in a position where I can expand the tests and test the board further.

One closing thought on JTAG and boundary scan. Recently, I was contacted by someone on LinkedIn asking for a little help with the AUP board from Tria. He had a simple flashing LED design but could not get his board to connect and program.

The board was a loaner, and who knows how it had been looked after in the past. Development boards tend to have harsh lives. A JTAG or boundary scan test over the USB FTDI JTAG connector to prove the development board is functional can again save a lot of development time and worry.

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Workshops and Webinars:

If you enjoyed the blog why not take a look at the free webinars, workshops and training courses we have created over the years. Highlights include:

Upcoming Webinars Timing, RTL Creation, FPGA Math and Mixed Signal

Professional PYNQ Learn how to use PYNQ in your developments

Introduction to Vivado learn how to use AMD Vivado

Ultra96, MiniZed & ZU1 three day course looking at HW, SW and PetaLinux

Arty Z7-20 Class looking at HW, SW and PetaLinux

Mastering MicroBlaze learn how to create MicroBlaze solutions

HLS Hero Workshop learn how to create High Level Synthesis based solutions

Perfecting Petalinux learn how to create and work with PetaLinux OS

Boards

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Adiuvo Embedded System Development board - Embedded System Development Board

Adiuvo Embedded System Tile - Low Risk way to add a FPGA to your design.

SpaceWire CODEC - SpaceWire CODEC, digital download, AXIS Interfaces

SpaceWire RMAP Initiator - SpaceWire RMAP Initiator, digital download, AXIS & AXI4 Interfaces

SpaceWire RMAP Target - SpaceWire Target, digital download, AXI4 and AXIS Interfaces

Other Adiuvo Boards & Projects.

**Embedded System Book **** **

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