Over the past year Intel engineers have worked a lot on Cache Aware Scheduling for the Linux kernel. The yet-to-be-merged functionality allows for the Linux kernel to better aggregate tasks sharing data to the same last level cache (LLC) domain to reduce cache misses and cache bouncing. The Cache Aware Scheduling development was led by Intel but helps other CPU vendors too for processors with multiple cache domains. Back in October I showed some nice performance wins for AMD EPYC Turin with Cache Aware Scheduling while today’s article are some benchmarks of the newest CAS code and looking at the performance benefit on Xeon 6 “Granite Rapids” processors.