🏛️ Embassy - hello · Scour

Rust async combinators for elegant and secure concurrency

kerkour.com·14h·

Discuss: r/rust

Prisma 7: Rust-Free Architecture and Performance Gains

infoq.com·1d·

Discuss: Hacker News

Modernizing Legacy C Systems: Safe Rust Integration Without Complete Rewrites

dev.to·6h·

Discuss: DEV

⚠️Rust Unsafe

CPU-less parallel execution of lambda calculus in digital logic

arxiv.org·15h

🔓Lock-Free Programming

ra0x3/mcpkit-rs: PoC MCP WebAssembly (WASM) integration, forked from the official Rust SDK for the Model Context Protocol

github.com·4h·

Discuss: Hacker News

🕸️WebAssembly

Scientific Computing in Rust Monthly #14

scientificcomputing.rs·8h

🦀Rust Macros

Jackpoint: control Claude via Matrix DMs

piszek.com·3h

ES6 Generators Deliver Go Style Concurrency

swannodette.github.io·18h

SHADOW: Simultaneous Multi-Threading Architecture with Asymmetric Threads

danglingpointers.substack.com·1d·

Discuss: Substack

🧵Lightweight Threads

FlashAttention 4: Faster, Memory-Efficient Attention for LLMs

digitalocean.com·8h

🔄Hardware Transactional Memory

Building scalable agentic assistants: A graph-based approach

thenewstack.io·2h

Clockworker: single-threaded async executor with powerful scheduling to sit on top of async runtimes

github.com·1d·

Discuss: r/rust

⚡Tokio Runtime

blog.lambdaclass.com·5h

Building live collaboration in Rust for millions of users, part 1

photoroom.com·2d·

Discuss: Hacker News

Pushing the Packed SIMD Extension Over the Line: An Update on the Progress of Key RISC-V Extension

semiwiki.com·1d

Designing a Programming Language for the Desert

futhark-lang.org·4h·

Discuss: Hacker News

🔨Incremental Compilation

TigerBeetle vs PostgreSQL Performance: Benchmark Setup, Local Tests

softwaremill.com·1d

🐅TigerBeetle Protocol

Red Macros Factory Is Joining OST (And So Am I!)

outflank.nl·4h

🦀Rust Macros

Tips for Using GitHub Copilot's Agent Mode

incrementsofincrements.bearblog.dev·3h

💬Prompt Engineering

A Novel Side-channel Attack That Utilizes Memory Re-orderings (U. of Washington, Duke, UCSC et al.)

semiengineering.com·1h

🔄Hardware Transactional Memory

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