Binary search, branching and Eytzinger layout
en.algorithmica.org·3w·
Discuss: Hacker News
🧠CPU Architecture
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DeepPrune: Parallel Scaling without Inter-trace Redundancy
dev.to·2w·
Discuss: DEV
⚡SIMD
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High-Performance Tiered Memory Pool for Go with Weak References and Smart Buffer Splitting
github.com·2w
⚙️Compilers
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Architectural Leakage Analysis of Masked Cryptographic Software on RISC-V Cores
eprint.iacr.org·2w
⚙️Compilers
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Building a Redis Clone in Zig—Part 2
charlesfonseca.substack.com·3w·
Discuss: r/programming
⚡SIMD
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Myths Programmers Believe about CPU Caches
software.rajivprab.com·6d·
Discuss: Hacker News
🧠CPU Architecture
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Skia: Exposing Shadow Branches
dl.acm.org·2w·
Discuss: Hacker News
🧠CPU Architecture
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Flat Combining: A Simple Rust Experiment
khayyamguliyev.substack.com·1w·
Discuss: Substack
🌐WebAssembly
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Low-Level Hacks
blog.raycursive.com·2d·
Discuss: Hacker News
🌐WebAssembly
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News for October 2025
ptreview.sublinear.info·2d
🏗️Constructive Mathematics
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Attention Is All You Need for KV Cache in Diffusion LLMs
paperium.net·2d·
Discuss: DEV
🧠CPU Architecture
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Rethinking PostgreSQL buffer mapping for modern hardware architectures
orioledb.com·3w·
Discuss: Hacker News
🧠CPU Architecture
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Optimizable Code (2013)
deplinenoise.wordpress.com·2w·
Discuss: Hacker News
🧠CPU Architecture
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An enough week
blog.mitrichev.ch·3w·
Discuss: blog.mitrichev.ch
⚡SIMD
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Why do CPUs have multiple cache levels?
fgiesen.wordpress.com·3w·
Discuss: Hacker News
🧠CPU Architecture
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Hashing multiple blobs with BLAKE3
iroh.computer·3w
⚡SIMD
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A deep dive into BPF LPM trie performance and optimization
blog.cloudflare.com·2w·
Discuss: Lobsters, Hacker News
🧠CPU Architecture
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Thoughts on "Static Retrival Revisited"
curiouscoding.nl·2d
🔐Cryptography
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Moving past speculation: How deterministic CPUs deliver predictable AI performance
venturebeat.com·4d
🧠CPU Architecture
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Rust Atomics and Locks: Out-of-Thin-Air
marabos.nl·2w·
Discuss: r/rust
🌐WebAssembly
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