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💾 Cache Design
LRU, Eviction Policies, Hit Rates, Memory Hierarchy
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81707
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DualMap
: Enabling Both Cache
Affinity
and Load Balancing for Distributed LLM Serving
arxiv.org
·
21h
🧮
Algorithms
Performance Tip of the Week #62:
Identifying
and reducing memory
bandwidth
needs
abseil.io
·
2d
🧮
Algorithms
The Avatar Cache:
Enabling
On-Demand Security with
Morphable
Cache Architecture
arxiv.org
·
21h
🧮
Algorithms
Caching
in 2026: Fundamentals,
Invalidation
, and Why It Matters More Than Ever
lukasniessen.medium.com
·
1d
·
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r/node
🧮
Algorithms
Enhancement
on
Caching
and Service Workers
dev.to
·
2d
·
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DEV
🔍
Search engines
LocalGPT
: A local AI assistant with
persistent
memory in a single binary
localgpt.app
·
7h
·
Discuss:
Hacker News
🤖
AI
Three Cache
Layers
Between Select and
Disk
frn.sh
·
12h
·
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Hacker News
,
r/programming
🧮
Algorithms
the
mathematics
of
compression
in database systems
bitsxpages.com
·
7h
🧮
Algorithms
Lucene
HNSW
performance: A deep dive into the OS page cache
opensearch.org
·
5h
🧮
Algorithms
Show HN: Model Training Memory
Simulator
czheo.github.io
·
1d
·
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Hacker News
📈
Machine Learning
Everything I know about good system design
seangoedecke.com
·
1h
👩💻
Programming
CPUs
are Back: The
Datacenter
CPU Landscape in 2026
newsletter.semianalysis.com
·
7h
·
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r/hardware
🧮
Algorithms
Designing a
Drift-Resistant
Memory System for LLMs
dev.to
·
3d
·
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DEV
👩💻
Programming
John
Carmack
muses
using a long fiber line as as an L2 cache for streaming AI data — programmer imagines fiber as alternative to DRAM
tomshardware.com
·
5h
·
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Hacker News
👩💻
Programming
Hitting
1,000
tokens
per second on a single RTX 5090
blog.alpindale.net
·
1d
·
Discuss:
Hacker News
,
Hacker News
🧮
Algorithms
Heterogeneous
Processing: A Strategy for
Augmenting
Moore's Law (2006)
linuxjournal.com
·
1d
·
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Hacker News
🧮
Algorithms
AI's GPU problem is actually a data
delivery
problem
venturebeat.com
·
21h
🤖
AI
A Note on
Flat
Abstract
Syntax
Trees
gist.github.com
·
8h
·
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Hacker News
🧮
Algorithms
NVMe
Zoned
Namespaces
(ZNS) Devices
zonedstorage.io
·
17h
⚡
Performance
Intel Core Ultra "Arrow Lake Refresh" Chips Focus on E-core Count and
L3
Cache
Uplifts
techpowerup.com
·
9h
⚡
Performance
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