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Assembly Language
⚡ Assembly Language
x86, ARM, CPU Architecture, Low-Level Optimization
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Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
⚡
CPU Architecture
phoronix.com
·
1d
1 day ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
Breaking
architecture
barriers: Running
x86
games and apps on
ARM
(gpn24)
⚡
CPU Architecture
cdn.media.ccc.de
·
3d
3 days ago
Actions for Breaking architecture barriers: Running x86 games and apps on ARM (gpn24)
(PR) NextSilicon to Productize Arbel
RISC-V
Core Into 64-Core Enterprise Processor for AI and HPC
⚡
CPU Architecture
techpowerup.com
·
8h
8 hours ago
Actions for (PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC
SpacemiT shows off usably quick
RISC-V
mini desktop
⚡
CPU Architecture
Content type:
News
theregister.com
·
12h
12 hours ago
Actions for SpacemiT shows off usably quick RISC-V mini desktop
RISC-V
Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
🏗
Computer Architecture
Content type:
News
eetimes.com
·
2d
2 days ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
RISC-V
And GPU Synergy In Practice: A Path Towards High-Performance SoCs
⚡
CPU Architecture
semiengineering.com
·
6d
6 days ago
Actions for RISC-V And GPU Synergy In Practice: A Path Towards High-Performance SoCs
Fast Exact Nearest-Neighbor Learning for High-Frequency Financial Time Series
🤖
Machine Learning
Content type:
Academic
arxiv.org
·
17h
17 hours ago
Actions for Fast Exact Nearest-Neighbor Learning for High-Frequency Financial Time Series
Intel introduced ‘the first processor in the
x86
series and the first 8086 microprocessor’ on this day in 1978 —
CPU
was designed as a temporary substitute for the delayed iAPX 432 project
⚡
CPU Architecture
Content type:
News
tomshardware.com
·
2d
2 days ago
Actions for Intel introduced ‘the first processor in the x86 series and the first 8086 microprocessor’ on this day in 1978 — CPU was designed as a temporary substitute for the delayed iAPX 432 project
"
RISC-V
Is Now"
🏗
Computer Architecture
Content type:
Video
youtube.com
·
1d
1 day ago
·
Hacker News
Actions for "RISC-V Is Now"
If a decade-old Nintendo Switch can run PC games, your next handheld doesn't need to be
x86
⚡
CPU Architecture
xda-developers.com
·
21h
21 hours ago
Actions for If a decade-old Nintendo Switch can run PC games, your next handheld doesn't need to be x86
jeffhuen/RustyCSV: High-performance CSV parsing for Elixir. Rust NIF with
SIMD
acceleration, parallel parsing, and bounded-memory streaming. Drop-in NimbleCSV replacement.
🌊
Stream Processing
Content type:
Code
github.com
·
4d
4 days ago
·
Hacker News
Actions for jeffhuen/RustyCSV: High-performance CSV parsing for Elixir. Rust NIF with SIMD acceleration, parallel parsing, and bounded-memory streaming. Drop-in NimbleCSV replacement.
RISC-V
edge box packs dual GbE, CAN, and 4G/5G support
⚡
CPU Architecture
linuxgizmos.com
·
2d
2 days ago
Actions for RISC-V edge box packs dual GbE, CAN, and 4G/5G support
Why my
SIMD
code was silently running as scalar, and what debugging it taught me about production environment assumptions
⚙️
Systems Programming
Content type:
Blog
coloneltoad.substack.com
·
6d
6 days ago
·
Substack
Actions for Why my SIMD code was silently running as scalar, and what debugging it taught me about production environment assumptions
Why
x86
Zeroes a
Register
With `xor eax, eax`
⚡
CPU Architecture
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
Open Source Hardware Certifications for May 2026
⚡
CPU Architecture
makezine.com
·
2d
2 days ago
Actions for Open Source Hardware Certifications for May 2026
SWIFT: Shallow and
SIMD-Aware
CKKS Functional Bootstrapping for
Low-Latency
⚙️
CPU Microarchitecture
eprint.iacr.org
·
6d
6 days ago
Actions for SWIFT: Shallow and SIMD-Aware CKKS Functional Bootstrapping for Low-Latency
Linux 7.2 To Enable ESWIN SoC Support By Default For
RISC-V
Kernel Builds
🏗
Computer Architecture
phoronix.com
·
3h
3 hours ago
Actions for Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
The Boot Chain of a
RISC-V
Board: From Silicon to Ubuntu 26.04
⚡
CPU Architecture
Content type:
Blog
blog.ludovic.dev
·
2d
2 days ago
·
Hacker News
,
Hacker News
Actions for The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04
AMD Hits Record
X86
CPU
Market Share as Intel Supply Stalls in Q1
⚡
CPU Architecture
hothardware.com
·
6d
6 days ago
Actions for AMD Hits Record X86 CPU Market Share as Intel Supply Stalls in Q1
x86CSS: a working CSS-only
x86
CPU/emulator/computer
⚡
CPU Architecture
osnews.com
·
3d
3 days ago
Actions for x86CSS: a working CSS-only x86 CPU/emulator/computer
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