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Performance
🚀 Performance
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Benchmarking, Profiling, Optimization, Bottlenecks
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94
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Systems Programming
6it.dev
·
3d
3 days ago
Efficient C++ Programming for Modern C++ CPUs, Chapter 4/part 2
Discussed on
Hacker News
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Actions for Efficient C++ Programming for Modern C++ CPUs, Chapter 4/part 2
🎯
Escape Analysis
Azul
·
15h
15 hours ago
Your JVM Is an AWS Architecture Decision – Which Most Teams
Miss
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Actions for Your JVM Is an AWS Architecture Decision – Which Most Teams Miss
⚡
CPU Architecture
arXiv
·
5h
5 hours ago
When Is a Columnar Scan
Bandwidth-Bound
? A
Decode-Throughput
Law and Its Cross-Hardware Validation
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Actions for When Is a Columnar Scan Bandwidth-Bound? A Decode-Throughput Law and Its Cross-Hardware Validation
⚡
SIMD Optimization
Red Hat Developer
·
1d
1 day ago
Designing distributed AI inference: Core concepts and scaling dimensions
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Actions for Designing distributed AI inference: Core concepts and scaling dimensions
📊
Profiling Tools
GitHub
·
19h
19 hours ago
SiliconScope: Local-AI Cockpit for Apple Silicon
Discussed on
Hacker News
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Actions for SiliconScope: Local-AI Cockpit for Apple Silicon
⚡
Hardware Acceleration
HotHardware
·
2d
2 days ago
SK Hynix Fires Back In The AI
Memory
Race With Next Gen 48GB HBM4E
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Actions for SK Hynix Fires Back In The AI Memory Race With Next Gen 48GB HBM4E
⚡
performance
thecybersidekick.beehiiv.com
·
4d
4 days ago
AI Inference at the Edge: Running Real-Time LLMs in Kubernetes Without a GPU Farm
Discussed on
DEV
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Actions for AI Inference at the Edge: Running Real-Time LLMs in Kubernetes Without a GPU Farm
⚡
CPU Architecture
TechSpot
·
20h
20 hours ago
Intel and AMD are teaming up to make x86 CPUs better at AI, without needing a GPU
Covers
Intel and AMD's new ACE CPU extensions bring an efficient AI-oriented instruction set to x86 — a new design makes matrix multiplication more power- and density-...
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Actions for Intel and AMD are teaming up to make x86 CPUs better at AI, without needing a GPU
⚙️
Systems Programming
EE Times
·
2h
2 hours ago
CEA-Leti CEO: AI’s Real
Bottleneck
Is Architecture
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Actions for CEA-Leti CEO: AI’s Real Bottleneck Is Architecture
⚡
Hardware Acceleration
Posts by Year
·
1d
1 day ago
Mac Studio: The Best Local LLM Workstation Money Can(‘t) Buy
Covers
7 stories
See all stories this covers
including
Introducing Claude Opus 4.8
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Actions for Mac Studio: The Best Local LLM Workstation Money Can(‘t) Buy
💾
Cache Optimization
platformengineering.org
·
4d
4 days ago
Three hidden GKE
optimization
opportunities unlocked by Google Cloud VM modernization (5 minute read)
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Actions for Three hidden GKE optimization opportunities unlocked by Google Cloud VM modernization (5 minute read)
⚡
Hardware Acceleration
gamespot.com
·
12h
12 hours ago
AMD’s FSR Upscaling 4.1 Comes To Older GPUs, Steam Machine And Xbox ROG Ally Support On The Way
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Actions for AMD’s FSR Upscaling 4.1 Comes To Older GPUs, Steam Machine And Xbox ROG Ally Support On The Way
⚡
CPU Architecture
Tom's Hardware
·
1d
1 day ago
M3 MacBook Air plunges to $799 in early Amazon Prime Day sale — 38% discount blows the MacBook Neo out of the water
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Actions for M3 MacBook Air plunges to $799 in early Amazon Prime Day sale — 38% discount blows the MacBook Neo out of the water
🦀
Rust Macros
zarxhnebula.medium.com
·
6d
6 days ago
I Wrote 30 Lines of C and Watched My
CPU
Leak Secrets
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Actions for I Wrote 30 Lines of C and Watched My CPU Leak Secrets
⚡
Hardware Acceleration
The Register
·
15h
15 hours ago
Nvidia gets all agentic about supercomputing for scientific research
Covered by
contextmaestro.com
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Actions for Nvidia gets all agentic about supercomputing for scientific research
⚡
Hardware Acceleration
igor´sLAB
·
1d
1 day ago
AMD Medusa Point: Zen 6 appears as an early 10-core sample in Geekbench
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Actions for AMD Medusa Point: Zen 6 appears as an early 10-core sample in Geekbench
⚡
Hardware Acceleration
vettedconsumer.com
·
5d
5 days ago
Prompt processing vs. generation: two phases, opposite
bottlenecks
Covers
Efficient Memory Management for Large Language Model Serving with PagedAttention
Discussed on
Hacker News
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Actions for Prompt processing vs. generation: two phases, opposite bottlenecks
⚡
CPU Architecture
TechRadar
·
10h
10 hours ago
A server within a server: HP packs 81,920
CPU
cores, up to 1.28PB RAM into one 42U rack using 80 multi-node motherboards — unannounced Venice is likely to be
th
...
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Actions for A server within a server: HP packs 81,920 CPU cores, up to 1.28PB RAM into one 42U rack using 80 multi-node motherboards — unannounced Venice is likely to be th...
⚡
Hardware Acceleration
Network World
·
12h
12 hours ago
Nvidia unveils Vera Rubin Platform targeting AI, HPC infrastructure customers
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Actions for Nvidia unveils Vera Rubin Platform targeting AI, HPC infrastructure customers
🦀
Rust Async
dev-to-uploads.s3.us-east-2.amazonaws.com
·
2d
2 days ago
Stripping Away Abstractions: How I Built a Rust
Microkernel
from Scratch in 100 Hours (At Age 13)
Discussed on
DEV
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Actions for Stripping Away Abstractions: How I Built a Rust Microkernel from Scratch in 100 Hours (At Age 13)
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