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Scoured 204922 posts in 38.5 ms
Lessons Learned Building High-Performance Rust Profiler  📦uv
pawelurbanek.com·5d·Hacker News, r/rust
nviennot/core-to-core-latency: Measures the latency between CPU cores  ⚡CPU Architecture
github.com·5d·Hacker News
Closer in the Gap: Towards Portable Performance on RISC-V Vector Processors  ⚙️Systems Programming
arxiv.org·5d
Cache Stampede Prevention in Go — 1k req/s load test + full monitoring stack  🔭OpenTelemetry
github.com·6d·r/golang
HyDRA: Deadline and Reuse-Aware Cacheability for Hardware Accelerators  ⚡CPU Architecture
arxiv.org·5d
NoNaeAbC/std_simd: I played around with std::simd  💻Terminal Emulators
github.com·3d·Hacker News, Hacker News
RDKV: Rate-Distortion Bit Allocation for Joint Eviction and Quantization of the KV Cache  📊Columnar Storage
arxiv.org·5d
REPTILES: Repeated Tiles of Sargantana, a RISC-V multicore based on OpenPiton  ⚙️Systems Programming
arxiv.org·5d
KV-RM: Regularizing KV-Cache Movement for Static-Graph LLM Serving  📊Columnar Storage
arxiv.org·5d
When Does Value-Aware KV Eviction Help? A Fixed-Contract Diagnostic for Non-Monotone Cache Compression  📊Columnar Storage
arxiv.org·5d
RateQuant: Optimal Mixed-Precision KV Cache Quantization via Rate-Distortion Theory  🏗️System Design
arxiv.org·6d
FibQuant: Universal Vector Quantization for Random-Access KV-Cache Compression  🔍Vector Search
arxiv.org·4d
TLX: Hardware-Native, Evolvable MIMW GPU Compiler for Large-scale Production Environments  ⚙️Systems Programming
arxiv.org·5d·Hacker News
TransDot: An Area-efficient Reconfigurable Floating-Point Unit for Trans-Precision Dot-Product Accumulation for FPGA AI Engines  💻Terminal Emulators
arxiv.org·6d
HE-PIM: Demystifying Homomorphic Operations on a Real-world Processing-in-Memory System  📊Columnar Storage
arxiv.org·3d
FractalSortCPU: Bandwidth-Efficient Compressed Radix Sort on CPU  📊Columnar Storage
arxiv.org·5d·Hacker News
Janus: Compiler-Based Defense Against Transient Execution Attacks Using ARM Hardware Primitives  ⚙️Systems Programming
arxiv.org·5d
CCD-Level and Load-Aware Thread Orchestration for In-Memory Vector ANNS on Multi-Core CPUs  🔍Vector Databases
arxiv.org·5d
EULER-ADAS: Energy-Efficient & SIMD-Unified Logarithmic-Posit Engine for Precision-Reconfigurable Approximate ADAS Acceleration  ⚡CPU Architecture
arxiv.org·6d
Stencil Computations on Cerebras Wafer-Scale Engine  ⚙️Systems Programming
arxiv.org·6d
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