eyengin/xv6-riscv-unmatched: A port of xv6-riscv to the SiFive HiFive Unmatched board.
github.com·1d·
Discuss: Hacker News
🧩RISC-V Assembly
Preview
Report Post

xv6-riscv for HiFive Unmatched

This is a port of xv6-riscv to the SiFive HiFive Unmatched board (FU740). See notes for the implementation details.

Highlights

  • Stability on actual hardware: usertests passed, resolving hardware-specific issues.
  • Direct M-mode boot via U-Boot SPL: Replaced the standard OpenSBI with xv6 kernel, leveraging SPL for hardware initialization and minimizing kernel modifications.
  • SD card driver: Ported the SPI mode SD card driver (from SiFive sources) to replace VirtIO.

Status

  • Boot setup
  • UART output
  • SD card driver
  • Pass usertests
  • Validate via 6.1810 labs (local validation only; solutions will not …

Similar Posts

Loading similar posts...

Keyboard Shortcuts

Navigation
Next / previous item
j/k
Open post
oorEnter
Preview post
v
Post Actions
Love post
a
Like post
l
Dislike post
d
Undo reaction
u
Recommendations
Add interest / feed
Enter
Not interested
x
Go to
Home
gh
Interests
gi
Feeds
gf
Likes
gl
History
gy
Changelog
gc
Settings
gs
Browse
gb
Search
/
General
Show this help
?
Submit feedback
!
Close modal / unfocus
Esc

Press ? anytime to show this help