NEW APPROACH IN LATEST PCB DESIGN

The prior boards used an open collector NAND gate to generate the 80-100 ns pulse that represents a 1 bit at a given bit position in the addressed word of memory. When several positions had a 1 value, spurious retriggering would occur which produced a string of pulses rather than the single pulse that should be emitted during a read cycle.

The new approach places a discrete transistor as the open collector driver of the pulse, after being fed by an AND gate (since the transistor inverts, the NAND logic function must become an AND). This isolates the current sinking that occurs during the pulse and ensures a pure ground path for that current which comes from the IBM 1130 logic cards for the Storage Buffer Register.

I selected a transistor with very…

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