SCOPE SHOWS SPURIOUS RETRIGGERING DURING READS

The scope was set to trigger on the +STORAGE READ signal (yellow trace) activating. I displayed the sense output for the P1 parity bit (green trace) and P2 parity bit (purple trace), as well as the sense pulse for bit 15 (blue trace). Depending on the number of one bits in the stored data word - sense pulses are only generated when the bit value is 1 - I saw various amounts of retriggering occurring.

The time chain produces a pulse about 800 nanoseconds after the +STORAGE READ rising edge. That is what gates sense output pulses when the bit value is 1. Retriggering means that the timing chain produces additional pulses 800 nanoseconds after the first one. Those force the Storage Buffer Register to have 1 bits in every position where sense output pulse arrives, but the retriggered pulses will corrupt the register during unrelated cycles, causing the processor to work incorrectly.

My first display when I powered up was a word that had six bits of the word set to 1, thus generating six sense output pulses plus pulses on parity bits P1 and P2 for a total of eight. The scope showed me three retriggers, similar to the defective behavior I was seeing in the past.

I then stored a word of b0000000000000001 which has only one of the data bits with a 1 value. Parity bit P1 is a 1 because the left eight bits need to have an odd number of ones, while parity bit P2 is off because the right eight bits already have an odd number of ones. No retriggering occurred as you can see in the scope output below:

You can see that bit 15 (blue trace) has a pulse because the bit value is one, and the parity bits P1 and P2 are 1 and 0 respectively. No retriggering.

I then added a second bit so that the data word was b0000000000000011 producing sense pulses on bits 14 and 15. Both halves of the word have an even number of one bits, so both parity bits should be a one. That is what I observed, but now there is one retriggered pulse making the system misbehave.

We observe that the more sense pulses produced, the more spurious retriggering occurs. I moved the blue trace to the +3.3V rail of the PCB and watched it in AC mode so that I saw disturbances on the rail. The same case as above, the one with one retrigger, shows the same pattern on the 3.3V rail in the trace below:

The 3.3V line rings 1 to 1.5V peak to peak, with the peaks right at the time when the trigger and retrigger take place. I went back to the original case with six data bits of 1 and both parity bits at 1, but watched the 3.3V rail.

Now there are four rings rather than two, which are associated with the three spurious retriggers. I did a major rework of the PCB to address the voltage and ground rails to eliminate this kind of behavior. A ground and a 3.3V layer plus large traces and multiple vias carrying current from the power layers to the chip connections. I used multiple large stranded wires for the ground connection to the 1130. Decoupling capacitors were placed on the bottom of the PCB to place them as close to the VCC/ground pins as possible.

Each sense output pulse sinks about 8 ma of current from the 1130 system, thus the worst case of a word of all one bits would generate 18 pulses for a sink of 144 ma over a duration of about 100 nanoseconds. Each of the chips that produces the sense pulse handles four bits, thus that chip sinks 32ma of current from the 1130.

The chip is an open drain NAND gate which should not involve the 3.3V rail at all in the current being sunk - that should flow through the transistor to ground and back to the 1130. Unless there is something obscure inside the circuitry of the NAND gate that causes parasitic power consumption from VCC when the open drain transistor is sinking power from the 1130, this doesn’t seem like a likely cause.

When I test the output pulses with a pullup resistor on the workbench, there is no bounce but when I hook the PCB to the IBM 1130, there is all the current flowing through the transistors. I don’t see the rail ringing nor the retriggering on the workbench, only on the real machine, but that is probably because the current flowing on the workbench is much lower.

I am focusing on investigating ringing caused by the design of the PCB and circuit. It is possible to have the decoupling capacitors on a board create ringing if they reach a resonance at the frequency of the sense pulses. This would happen if the inductance, resistance and capacitance of the capacitors and the traces have values that line up to create strong resonant peaks.

If that is indeed what is happening, there are ways I can resolve this by changing component values or tweaking other aspects of the design. Since this is a new PCB version where I made very substantial changes to the traces, including rounding every change in direction to reduce reflections. the trace impedance values have to be pretty different, yet the ringing is the same. This suggest that it is the decoupling capacitors or the voltage regulator that is the root cause.