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In a warmly received keynote at the RISC-V Summit, computer architecture legend David Patterson took the audience on a captivating trip back to 1981, using scanned versions of his original overhead transparencies to recount the birth of Reduced Instruction Set Computing (RISC) at UC Berkeley.

Patterson began with humor, noting his wife’s love for time-travel movies and explaining how age allows easy travel backward. Digging through old files, he rediscovered those classic plastic slides—artifacts unfamiliar to much of the younger audience—and used them to recreate the talk he gave across campuses over four decades ago.

The computing landscape of February 1981 was starkly different: mainframes and minicomputers dominated serious work, with IBM as the undisputed leader. DEC’s VAX, a refrigerator-sized 32-bit minicomputer running at 5 MHz with a 2 KB cache, represented the pinnacle. The IBM PC had not yet launched, and Intel’s 8086 was the cutting-edge 16-bit microprocessor. Cultural markers included Ronald Reagan’s presidency, disco music, and the release of Raiders of the Lost Ark.

Against this backdrop, Complex Instruction Set Computers (CISC) reigned supreme. The prevailing philosophy held that richer, more varied instructions would close the “semantic gap” between high-level languages and hardware. Microprogramming, enabled by growing memory densities under Moore’s Law, made complex instructions seemingly inexpensive. Marketing reinforced the idea that sophistication meant smaller programs and greater reliability, while registers were dismissed as old-fashioned.

Reality proved otherwise. High-level language programming used only a small subset of instructions. Complex operations—such as the VAX’s array-indexing instruction or IBM 370’s multi-register moves—were often slower than sequences of simpler ones. Design cycles lengthened dramatically, and microcode bugs were rampant; Patterson’s 1979–1980 sabbatical at DEC exposed constant patching of VAX microcode.

These observations crystallized into RISC principles: favor simplicity unless a compelling reason exists; prioritize fast clock cycles, easy decoding, and pipelining over instruction count or program size; recognize that microcode offers no magic; and rely on advancing compiler technology.

To illustrate, Patterson, a car enthusiast, likened CISC to an over-ornamented 1950s Cadillac and RISC to a sleek, agile sports car.

The ideas gained traction with Patterson and student David Ditzel’s 1980 paper, “The Case for the Reduced Instruction Set Computer,” published alongside a rebuttal from VAX architects—sparking immediate controversy and lively RISC vs. CISC debates at conferences.

Berkeley proved the concept through graduate courses. Leveraging DARPA-funded CAD tools, a simplified instruction set, and sheer beginner’s luck, roughly a dozen students designed, laid out, fabricated, and tested RISC-I in under two years. Remarkably, the RISC-I instruction set closely resembles today’s RISC-V core—Patterson called RISC-V’s version slightly more elegant.

Porting Berkeley UNIX was straightforward, and early benchmarks showed the student-built RISC-I roughly twice as fast as the professional, multi-year VAX effort—a stunning validation.

Patterson closed by honoring the original team, including faculty Carlo Séquin and John Ousterhout, and graduate students. He shared photos from a 2015 ceremony installing a plaque for the first RISC microprocessor, where RISC-I pioneers met RISC-V leaders, creating a touching cross-generational moment.

Forty-five years later, the simplicity and elegance born in those Berkeley classrooms power billions of devices worldwide—and live on vibrantly in the open RISC-V ecosystem.

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