Introduction
**Traffic lights are a fundamental part of modern transportation systems.**They must operate in a strict and predictable sequence to ensure road safety and smooth traffic flow.
This project implements a Traffic Light Controller using a Finite State Machine (FSM) in Verilog HDL.The design is fully simulated and verified using Xilinx Vivado, without requiring any physical hardware.
Why this project?
The motivation behind this project was to understand how real-world control systems are implemented using digital logic.Traffic light controllers are a classic example of sequential systems, making them ideal for learning:
- Finite State Machine (FSM) design
- Clocked sequential logic
- Timing and control using counters
- RTL simulation a…
Introduction
**Traffic lights are a fundamental part of modern transportation systems.**They must operate in a strict and predictable sequence to ensure road safety and smooth traffic flow.
This project implements a Traffic Light Controller using a Finite State Machine (FSM) in Verilog HDL.The design is fully simulated and verified using Xilinx Vivado, without requiring any physical hardware.
Why this project?
The motivation behind this project was to understand how real-world control systems are implemented using digital logic.Traffic light controllers are a classic example of sequential systems, making them ideal for learning:
- Finite State Machine (FSM) design
- Clocked sequential logic
- Timing and control using counters
- RTL simulation and verificationThis project also serves as a strong foundation for more advanced designs such as communication protocols and embedded controllers.
Design Approach (How it works conceptually)
The controller is designed as a Moore-type Finite State Machine, where outputs depend only on the current state.
The FSM consists of three states:
- RED
- GREEN
- YELLOW
Each state remains active for a fixed duration controlled by an internal timer.State transitions occur synchronously on the rising edge of the clock, ensuring deterministic behavior.
On reset, the system always returns to the RED state, mimicking real-world traffic signal initialization.
Implementation Details (How it works technically)
The system is implemented in Verilog HDL and divided into the following logical blocks:
- State register to hold the current FSM state
- Timer logic to control state duration
- Output logic to drive traffic light signals
- A separate testbench to generate clock and reset signals
The testbench allows the design to be verified entirely through simulation.
Simulation & Verification
The design was verified using Vivado Behavioral Simulation.
The simulation waveform confirms:
- Correct reset behavior
- Proper state transitions (RED → GREEN → YELLOW → RED)
- Only one traffic light active at any time
This verifies the correctness of the FSM and timing logic.
STATE DIAGRAM
WAVEFORM
Future Enhancements
Possible future improvements include:
- Pedestrian signal integration
- Adaptive traffic timing using sensors
- Multi-intersection traffic control
- FPGA hardware implementation