In addition to AMD releasing the Ryzen AI Software 1.7 release on Friday, they also published a new version of their MLIR-AIE compiler toolchain for targeting AMD Ryzen AI NPU devices with this LLVM-based MLIR-focused stack.
The MLIR-AIE compiler allows generating Python code for execution on the Ryzen AI NPU and ultimately opens the door to other software targeting LLVM’s Multi-Level Intermediate Representation (MLIR). While Ryzen AI NPUs are a big focus these days, the toolchain also works for other AMD/Xilinx AI Engine devices such as their Versal SoCs.
The AMD MLIR-AIE 1.2 rel…
In addition to AMD releasing the Ryzen AI Software 1.7 release on Friday, they also published a new version of their MLIR-AIE compiler toolchain for targeting AMD Ryzen AI NPU devices with this LLVM-based MLIR-focused stack.
The MLIR-AIE compiler allows generating Python code for execution on the Ryzen AI NPU and ultimately opens the door to other software targeting LLVM’s Multi-Level Intermediate Representation (MLIR). While Ryzen AI NPUs are a big focus these days, the toolchain also works for other AMD/Xilinx AI Engine devices such as their Versal SoCs.
The AMD MLIR-AIE 1.2 release adds a Python 3.14 wheel, tile DMA WRITEBD support, updated install instructions, a new IRON host runtime abstraction layer, Windows Subsystem for Linux (WSL) compatibility work, various build updates, optimizing the Strix BF16 MATMUL performance, and a variety of fixes.
The new IRON host runtime abstraction aims to consolidate the run-time support into one implementation that can handle tracing, JIT, programming examples, and test cases. This deduplicates logic between the different runtime and helper code components, adds tracing capabilities to the JIT, improved caching, and other enhancements.
AMD MLIR-AIE 1.2 downloads and more information via the open-source project’s GitHub.