Intel engineer Tim Chen has sent out a second version of the proposed Cache Aware Scheduling patches for the Linux kernel to enhance the CPU performance of modern processors sporting multiple cache domains.

Cache Aware Scheduling aims to better Linux performance on modern CPUs by co-locating tasks sharing data to the same cache domain to enhance the cache locality and reducing cache misses and cache bouncing.

From their v2 patch message of the Cache Aware Scheduling benefits:

"[TL;DR]

Sappire Rapids: hackbench shows significant improvement when the number of different active threads is below the capacity of a LLC. schbench shows overall wakeup latency improvement. ChaCha20-xiangshan shows good throughput improvement.

Genoa: ChaCha20-xiangshan shows huge throughput improvement. No obvious difference is observed in hackbench/schbench /netperf/stream/stress-ng. Phoronix has tested v1 and shows good improvements in 33 cases."

Indeed some benchmarks I ran back in October on AMD EPYC Turin with the prior Cache Aware Scheduling patches were showing some very nice performance benefits. I’ll work on testing the v2 patches on some additional hardware as time allows.

As for the v2 patches, there is improved NUMA balancing and other changes:

"1. Align NUMA balancing and cache affinity by prioritizing NUMA balancing when their decisions differ. 2. Dynamically resize per-LLC statistics structures based on the LLC size. 3. Switch to a contiguous LLC-ID space so these IDs can be used directly as array indices for LLC statistics. 4. Add clarification comments. 5. Add 3 debug patches (not meant for merging). 6. Other changes to address feedbacks from review of v1 patch set."

Those interested can find the v2 patches on the LKML for undergoing the latest round of code review and testing. Hopefully this Cache Aware Scheduling support manages to make it into the mainline Linux kernel in 2026.