Dramatically reducing energy consumption while accelerating the processing of large amounts of data. This is the aim of the new chip developed by a group of researchers from the Department of Electronics, Information and Bioengineering – DEIB at the Politecnico di Milano, led by Professor Daniele Ielmini, and presented in the study published in the prestigious journal Nature Electronics, with the researcher Piergiulio Mannocci as the first author.
The work originated as part of the ANIMATE (ANalogue In-Memory computing with Advanced device TEchnology) project, which was awarded an ERC Advanced Grant in 2022. The goal of the ANIMATE project was to develop the technology for the device, the circuits and system architectures, and the set of applications to **validate…
Dramatically reducing energy consumption while accelerating the processing of large amounts of data. This is the aim of the new chip developed by a group of researchers from the Department of Electronics, Information and Bioengineering – DEIB at the Politecnico di Milano, led by Professor Daniele Ielmini, and presented in the study published in the prestigious journal Nature Electronics, with the researcher Piergiulio Mannocci as the first author.
The work originated as part of the ANIMATE (ANalogue In-Memory computing with Advanced device TEchnology) project, which was awarded an ERC Advanced Grant in 2022. The goal of the ANIMATE project was to develop the technology for the device, the circuits and system architectures, and the set of applications to validate the Closed-Loop In-Memory Computing (CL-IMC). The resulting chip makes use of in-memory computing, which aims to overcome a limitation of computers: the need to continuously move data between the memory and the processor. By eliminating this internal ‘traffic’, the systems become faster and more energy efficient.
The DEIB team has developed a fully integrated analogue accelerator, manufactured using CMOS (Complementary Metal-Oxide-Semiconductor) technology; the device uses two 64×64 arrays of programmable resistive memories, SRAM cells. The architecture is complemented by an innovative model of analogue processing that utilises components integrated in the chip such as operational amplifiers and analogue-to-digital converters.
The set allows the system to handle complex calculations directly in the structure of the memory, avoiding the need to move data to an external processor, thereby reducing calculation times to a significant extent. In tests, the chip achieved similar accuracy to conventional digital systems, but with lower power consumption, less computing latency and a smaller footprint on the silicon.
The study represents an important step towards more compact, faster and sustainable devices, opening up new perspectives for research and industry. Applications range from robotics to data centres and from navigation systems to advanced telecommunications networks, such as the 6G technologies of the future.