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Custom CPUs
🔧 Custom CPUs
CPU design, custom processor, HDL, homebrew CPU, microarchitecture
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Programming Domain-Specific
FPGA
Hardblocks from HLS: An
RTL
Blackbox Approach
🔧
Dev Tools
Content type:
Academic
arxiv.org
·
1d
1 day ago
Actions for Programming Domain-Specific FPGA Hardblocks from HLS: An RTL Blackbox Approach
Founding Engineer -
FPGA
,
RTL
, &
ASIC
Architect at Zettascale
🖥️
Operating Systems
ycombinator.com
·
5d
5 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
Exploring the Classic Xilinx XC5202-6PQ100I
FPGA
🎮
GPU Microarchitecture
hackster.io
·
7h
7 hours ago
Actions for Exploring the Classic Xilinx XC5202-6PQ100I FPGA
RISC-V
CPU
Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3
🕹️
Emulators
phoronix.com
·
23h
23 hours ago
Actions for RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3
RISC-V
Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
🕹️
Emulators
Content type:
News
eetimes.com
·
1d
1 day ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
Asics
to Spin Off Its Red-hot Onitsuka Tiger
Brand
in Company Split
🚀
Bootstrapping
Content type:
News
wwd.com
·
2h
2 hours ago
Actions for Asics to Spin Off Its Red-hot Onitsuka Tiger Brand in Company Split
RISC-V
And GPU Synergy In Practice: A Path Towards High-Performance SoCs
🕹️
Emulators
semiengineering.com
·
6d
6 days ago
Actions for RISC-V And GPU Synergy In Practice: A Path Towards High-Performance SoCs
geohot/fromthetransistor: From the Transistor to the Web Browser, a rough outline for a 12 week course
⚙️
Low-Level Programming
Content type:
Code
github.com
·
6h
6 hours ago
·
Hacker News
Actions for geohot/fromthetransistor: From the Transistor to the Web Browser, a rough outline for a 12 week course
Asics
running shoes are up to 42% off — I’
ve
handpicked 7 deals on shoes I’
ve
tested and recommend
🌐
Distributed Systems
tomsguide.com
·
2d
2 days ago
Actions for Asics running shoes are up to 42% off — I’ve handpicked 7 deals on shoes I’ve tested and recommend
SpacemiT shows off usably quick
RISC-V
mini desktop
🕹️
Emulators
Content type:
News
theregister.com
·
4h
4 hours ago
Actions for SpacemiT shows off usably quick RISC-V mini desktop
Asics
Sets Its Tiger Free: Onitsuka, the 38% Margin
Brand
, Becomes Its Own Company
🚀
Bootstrapping
easternherald.com
·
7h
7 hours ago
Actions for Asics Sets Its Tiger Free: Onitsuka, the 38% Margin Brand, Becomes Its Own Company
Apple Lisa Inside an
FPGA
- talk at VCF SW
🔍
Reverse Engineering
Content type:
Video
retrocomputingforum.com
·
2d
2 days ago
Actions for Apple Lisa Inside an FPGA - talk at VCF SW
RISC-V
profiles – why is RVA23 significant?
⚙️
ISA Design
Content type:
Blog
ubuntu.com
·
6d
6 days ago
Actions for RISC-V profiles – why is RVA23 significant?
"
RISC-V
Is Now"
🕹️
Emulators
Content type:
Video
youtube.com
·
21h
21 hours ago
·
Hacker News
Actions for "RISC-V Is Now"
Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
🕹️
Emulators
phoronix.com
·
1d
1 day ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
Ultrafast machine learning on
FPGAs
via Kolmogorov-Arnold Networks
🎮
GPU Microarchitecture
lemmy.ml
·
16h
16 hours ago
Actions for Ultrafast machine learning on FPGAs via Kolmogorov-Arnold Networks
Agilex 9
FPGAs
power COTS VPX boards
🏗️
s390x
edn.com
·
6d
6 days ago
Actions for Agilex 9 FPGAs power COTS VPX boards
Open Source Hardware Certifications for May 2026
🕹️
Emulators
makezine.com
·
1d
1 day ago
Actions for Open Source Hardware Certifications for May 2026
The Onitsuka Tiger story: From an octopus-inspired sole to a Nike link
🕹️
Emulators
channelnewsasia.com
·
3h
3 hours ago
Actions for The Onitsuka Tiger story: From an octopus-inspired sole to a Nike link
EstRTL: Functional Estimation Guided
RTL
Code Generation
🔧
Compilers
Content type:
Academic
arxiv.org
·
9h
9 hours ago
Actions for EstRTL: Functional Estimation Guided RTL Code Generation
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