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Scoured 144231 posts in 15.4 ms
Optimising a Pipelined RISC-V Core: From Naive Pipeline to Near-Superscalar Performance  🔧Custom CPUs
mummanajagadeesh.github.io·1d·Lobsters, Hacker News
Arch: An AI-Native Hardware Description Language for Register-Transfer Clocked Hardware Design  🔧Custom CPUs
arxiv.org·20h
Easy 6502 by skilldrick  ⚙️Low-Level Programming
jumplink.eu·6d·Lobsters
From SoC to System-in-Package: Transforming Automotive Compute with Multi-Die Integration  🔧Custom CPUs
semiwiki.com·7h
14sea/Cyclone_CRAM_Mapper: A physical-aware routing codec for Intel Cyclone IV FPGAs.  🔧Custom CPUs
github.com·2d·Hacker News
Powerful Multicompute  🛡️CHERI
volatco.github.io·2h·Hacker News
DeiMOS – A Superoptimizer for the MOS 6502  ⚙️Low-Level Programming
news.ycombinator.com·19h·Hacker News
Synthesis of RTL-based Characterization Programs for Fault Injection  🛡️CHERI
eprint.iacr.org·6d
SHA-256 Hardware Accelerator for MicroBlaze-V + Zybo 7000  🛡️CHERI
hackster.io·1d
RISC-V 101 – what is it and what does it mean for Canonical?  🛡️CHERI
ubuntu.com·8h·Hacker News
DeiMOS – A Superoptimizer for the MOS 6502  ⚙️Low-Level Programming
aransentin.github.io·1d·Hacker News, r/programming
Introduction to Compilers and Language Design  🔧Compilers
dthain.github.io·6d
How Much Linear Memory Access Is Enough?  ⚙️Low-Level Programming
solidean.com·10h·Hacker News
the value of a performance oracle  🪝eBPF
wingolog.org·1d·Lobsters, Hacker News
Beyond Static Analysis: Proving Automotive Cybersecurity and Functional Safety  📋Formal Methods
embedded.com·11h
Reinventing Embedded Memory: Solving The SRAM Scaling Wall  🛡️CHERI
semiengineering.com·6d
With the AGI CPU, Arm is launching its first data center chip and is making a direct entry into the server business  🔧Custom CPUs
igorslab.de·2d
Roc: Fast  🪝eBPF
roc-lang.org·13h·Hacker News
Optimal Circuit Synthesis of Linear Codes for Error Detection and Correction  🔧Compilers
arxiv.org·1d
Apple’s chip ‘binning’ explained: What is it and why does it matter?  🔧Custom CPUs
macworld.com·13h

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