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🔍 Chip Verification
RISC-V Testing, Hardware Validation, Formal Methods, SystemVerilog
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9991
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178.0
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Reverse Engineering the
Prom
for the
SGI
O2
mattst88.com
·
48m
·
Discuss:
Hacker News
🔍
Reverse Engineering
Cascading
Robustness Verification: Toward Efficient
Model-Agnostic
Certification
arxiv.org
·
3d
⚖️
Consensus Networks
From Prediction to
Compilation
: A Manifesto for
Intrinsically
Reliable AI
news.ycombinator.com
·
10h
·
Discuss:
Hacker News
🏗️
AI Infrastructure
InfraBuilder
: The
Deterministic
Hardware Architect
dev.to
·
15h
·
Discuss:
DEV
☁️
Serverless Rust
Build a
Compiler
in Five Projects
kmicinski.com
·
1d
🏭
Code Generation
Full-circle Test-driven
Firmware
Development with
OpenClaw
blog.adafruit.com
·
1d
·
Discuss:
Hacker News
🔌
Embedded Rust
wareya/pred
_
recdec
: Predicated LL (recursive descent) parser in pure rust
github.com
·
1h
·
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Hacker News
🦀
Rust Macros
Heterogeneous
Processing: A Strategy for
Augmenting
Moore's Law (2006)
linuxjournal.com
·
9h
·
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Hacker News
⚙️
CPU Microarchitecture
Deobfuscation
and Analysis of
Ring-1.io
back.engineering
·
4h
·
Discuss:
Hacker News
🔍
eBPF
I Built a 6
BIPS
JIT
in Five Months
unlikelyemphasis.substack.com
·
2d
·
Discuss:
Substack
⚙️
CPU Microarchitecture
Show HN:
Standardized
robot brain with
hardware
safety
news.ycombinator.com
·
7h
·
Discuss:
Hacker News
🧠
Neuromorphic Hardware
Intel Appears To Have Quietly
Sunset
"On Demand" Software
Defined
Silicon
phoronix.com
·
10h
·
Discuss:
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⚙
Risc-v
**Pulse‑Sequence Tuning for Fault‑Tolerant
Exponentiation
in
Shor
’s Algorithm on Transmon Qubits**
dev.to
·
1d
·
Discuss:
DEV
⚙️
CPU Microarchitecture
Unlocking core memories with
GoldSrc
engine and
CS
1.6 (2025)
danielbrendel.com
·
11h
·
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☁️
Serverless Rust
The
Verification
Conundrum
semiengineering.com
·
6d
🐛
Fuzzing
Boot
Sharc
+ DSP over
UART
embd.cc
·
6h
·
Discuss:
Hacker News
🔌
Microcontrollers
[DRIVERS] Intel Chipset/MEI/VMD/Serial IO/GNA/DTT/HID/PMT (
6xx/7xx/8xx
)
elevenforum.com
·
1d
📱
Laptops
A
Newbie
's First
Contribution
to (Rust for) Linux
blog.buenzli.dev
·
3h
·
Discuss:
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🦀
Rust Macros
An Analysis of User-space
Idle
State Instructions on
x86
Processors
danglingpointers.substack.com
·
3d
·
Discuss:
Substack
⚙️
CPU Microarchitecture
Production pain points and coordination patterns from building a
dual-orchestrator
(Claude + Kimi) system on Claude Code. 8 failure modes with specs and
invariants
.
gist.github.com
·
23h
·
Discuss:
Hacker News
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