Built for speed and precision

Introducing the LPU

Compiler and software-defined, single-core architecture removes traditional software complexity while continuous, token-based execution delivers consistent performance without tradeoffs. Every cycle is accounted for. No wasted operations, no unpredictable delays.

Single Core & On-Chip SRAM

The LPU integrates hundreds of MB of SRAM as primary weight storage (not cache), cutting latency and feeding compute units at full speed. This enables efficient tensor parallelism across chips, a practical advantage for fast, scalable inference.

Custom Compiler, Fully In Control

Groq’s purpose-built compiler enables static scheduling and deterministic execution, ensuring predictable performance at every scale.

Power Efficient

Air-cooled by design, Groq’s LPU and GroqRack require no complex cooling and power infrastructure, cutting operating costs and lowering environmental impact.

Direct Chip-to-Chip Connectivity

LPUs connect directly via a plesiosynchronous protocol, aligning hundreds of chips to act as a single core. The compiler predicts data arrival precisely, coordinating both compute and network scheduling without reliance on caches or switches.

Designed for inference. Not adapted for it.

Established in 2016 for inference, Groq is literally built different. It’s the only custom-built inference chip that fuels developers with the performance they need at a cost that doesn’t hold them back.