Samsung Demonstrates 3D Stacked FETs with Triple Nanosheet Channels at 42nm (opens in new tab)

Samsung Electronics' Semiconductor Research Center presented the paper “First Demonstration of 3D Stacked FETs at Gate Pitch of 42 nm Featuring Triple Stacked Nanosheet Channels for Advanced Logic Applications” at the 2026 VLSI Symposium, held from June 14–18.