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💻 Computer Architecture
CPU design, instruction set, pipeline, cache hierarchy
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186831
posts in
25.1
ms
AMMA
: A
Multi-Chiplet
Memory-Centric Architecture for Low-Latency 1M Context Attention Serving
🧠
Edge AI
arxiv.org
·
1d
Intel says software optimization can
hide
up to 30% gaming
CPU
performance
💾
Low-Level Code
videocardz.com
·
6d
Neuromorphic
, the other AI
processor
🧬
Neuromorphic
jonpeddie.com
·
1d
RightNow-AI/picolm
: Run a 1-billion parameter LLM on a $10 board with 256MB RAM
🧠
Edge AI
github.com
·
3d
PSA for
9950X3D
users on
CachyOS
: your games are probably not using 3D V-Cache
🖥️
Retro Computing
rmnr.net
·
4d
·
r/cachyos
Reimagining Kernel Generation at the
PTX
Layer: An LLM System Learning from
DSLs
to Outperform Them
🛠️
Compilers
standardkernel.com
·
3d
·
Hacker News
Caching
Beyond
Redis
: Real-World Strategies That Don’t Break Your System
💾
Low-Level Code
commitlog.cc
·
6d
·
r/SoftwareEngineering
,
r/programming
Intel’s
CPU
supply is
recovering
just in time for the agentic AI wave
🧬
Neuromorphic
pcworld.com
·
6d
New
CPU
Memory
Module
💾
Low-Level Code
semiengineering.com
·
2d
How Pizza Tycoon
Simulates
Traffic on a 25
MHz
CPU
💾
Low-Level Code
hackaday.com
·
3d
You don't need an
expensive
GPU to run a local LLM that actually works
💾
Low-Level Code
xda-developers.com
·
1d
AI-Driven CPU Shortage
Saves
Intel’s Financial
Cookies
🧠
Edge AI
nextplatform.com
·
3d
High AI performance: New
RISC-V
SBC
is a powerful Raspberry Pi 5 alternative
🖥️
Microcontrollers
notebookcheck.net
·
4d
Random Site of the Week:
Ken
Shirriff
's blog
🖥️
Retro Computing
righto.com
·
4d
Hardware Generation and Exploration of
Lookup
Table-Based
Accelerators
for 1.58-bit LLM Inference
💾
Low-Level Code
arxiv.org
·
2d
SAM 2
Segmentation
3x
Slower
Than SAM? Fix Pipeline
💾
Low-Level Code
tildalice.io
·
5d
Memristive
crossbar
array-based hardware framework for compressed sensing and event-driven neuromorphic processing
🧬
Neuromorphic
nature.com
·
5d
Signal-folding-based
neuromorphic
hardware for energy-efficient computing
🧬
Neuromorphic
nature.com
·
3d
Assuring
Comprehensive
Security Coverage In Hardware Design
✅
Formal Verification
semiengineering.com
·
1d
Arm
C1-Ultra
Scheduling Model Merged For
LLVM/Clang
23
⚙️
LLVM
phoronix.com
·
6d
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