🚀 Performance Engineering - scribe · Scour

From 800ms to ~25ms: harness-driven optimization of a CUDA matmul kernel 📡Meshtastic

github.com·6d·Hacker News

Why Low-Latency Infrastructure Matters More Than Raw Specs 📡Meshtastic

cdrinfo.com·2d

STLGT: A Scalable Trace-Based Linear Graph Transformer for Tail Latency Prediction in Microservices 📈Graph Algorithms

Early tests show minimal performance impact from new budget HUDIMM DDR5 memory 🧑‍💻Computer Science

techspot.com·1h

Announcing Arm Performix: Empowering developers with scalable performance for the age of AI agents ⚡Productivity

newsroom.arm.com·2d·Hacker News

Odysseys: Benchmarking Web Agents on Realistic Long Horizon Tasks ⚡Productivity

odysseys-website.pages.dev·23h·Hacker News

Java Performance Tuning and Event-Driven System Design for Scalable Systems 🏗️Software Architecture

·6d

Continually improving our agent harness 🔢Incremental Games

Optimization vs. Architecture: Knowing the Difference 🏗️Software Architecture

tigerdata.com·1d

Intel prioritizes Xeon; CPU shortage opens door for AMD and MediaTek 🏹Arch Linux

digitimes.com·5h

Ethernet Commoditizes Everything. Except EOS 📡Meshtastic

routerjockey.com·14h·Hacker News

Boosting speed: Use eBPF and netstacklat to troubleshoot latency 📡Meshtastic

developers.redhat.com·1d

The Two Thread IDs of macOS: Measuring P/E Core Usage on Apple Silicon ⚡Productivity

bazhenov.me·6d

Best Practices for inference on Edge AI MCUs 🧩Cellular Automata

embedded.com·22h

Bun’s Zig fork got 4x faster compilation times ⚡Zig

ASUS AEMP lets users optimize mixed JEDEC DDR5 memory kits without XMP on Intel Z890 and B860 boards 🖥️PC Building

tweaktown.com·18h

Difference between revisions of "Boot Time Presentations" 🏹Arch Linux

PCIe 7.0 fundamentals: Baseline ordering rules 🖥️PC Building

NGINX Performance tuning 🦀Rust

gist.github.com·9h

Polling Rate, Latency, and the Future of Input: Between Marketing Promises and Measurable Reality (Continued, Part 2 of 2) 📝Note-Taking

igorslab.de·1d

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