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CPU Microarchitecture
🔬 CPU Microarchitecture
pipeline, out-of-order execution, branch prediction, IPC
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25
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ms
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
🔁
LICM
Content type:
Academic
arxiv.org
·
22h
22 hours ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
The Tick-Tock AI Development Cycle.
📊
Liveness Analysis
wilsoniumite.com
·
5h
5 hours ago
Actions for The Tick-Tock AI Development Cycle.
How much do amd64
microarchitecture
levels
help in Go?
⚡
SIMD Vectorization
Content type:
Blog
lemire.me
·
4d
4 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
Why x86 Zeroes a
Register
With `xor eax, eax`
🚀
Superscalar
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
Intel 8086, the First x86 chip, Enters its 50th Year in 2027
⚡
Hardware Transactional Memory
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
Advanced Vector Extensions 512 Acceleration of LSH and LEA-GCM
⚡
SIMD Vectorization
eprint.iacr.org
·
6d
6 days ago
Actions for Advanced Vector Extensions 512 Acceleration of LSH and LEA-GCM
Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
🎮
GPU Scheduling
openjdk.org
·
1d
1 day ago
·
r/java
Actions for Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
ARM MTE & Apple MIE: How Hardware Memory Tagging Reveals Invisible iOS Kernel Vulnerabilities
🛡️
Memory Safety
Content type:
Blog
jamf.com
·
8h
8 hours ago
Actions for ARM MTE & Apple MIE: How Hardware Memory Tagging Reveals Invisible iOS Kernel Vulnerabilities
Founding
Engineer
- FPGA, RTL, & ASIC Architect at Zettascale
⚙️
Kernel Dev
ycombinator.com
·
6d
6 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
Apple Chip Architecture from 1977 to 2026
🚀
Superscalar
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
1d
1 day ago
Actions for Apple Chip Architecture from 1977 to 2026
Fractal OS Lets Security Researchers See What Their CPUs Really Do
🚀
Superscalar
Content type:
News
spectrum.ieee.org
·
1d
1 day ago
Actions for Fractal OS Lets Security Researchers See What Their CPUs Really Do
Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
🔍
Search Indexing
Content type:
Blog
elastic.co
·
5d
5 days ago
Actions for Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
Dew Drop - June 8, 2026 (#4685)
📦
In-process Databases
alvinashcraft.com
·
2d
2 days ago
Actions for Dew Drop - June 8, 2026 (#4685)
The last bit –
Part
3
🔁
LICM
thinkingeek.com
·
4d
4 days ago
Actions for The last bit – Part 3
x1colegal/USTP-Secure: Secure (with AEAD) version of USTP, called USTP-Secure (ustps://)
🔀
Out-of-Order Execution
Content type:
Code
github.com
·
1d
1 day ago
·
Hacker News
Actions for x1colegal/USTP-Secure: Secure (with AEAD) version of USTP, called USTP-Secure (ustps://)
What Arm-based innovations happened in May 2026?
📊
Profiling
Content type:
Blog
newsroom.arm.com
·
5d
5 days ago
Actions for What Arm-based innovations happened in May 2026?
Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was
🚀
High Performance
theregister.com
·
6d
6 days ago
Actions for Intel's mysterious new datacenter GPU is what Nvidia's Rubin CPX nearly was
Aging
Mice
Became Stronger When Scientists Boosted One Protein
⏱️
TSC Calibration
sciencealert.com
·
5d
5 days ago
Actions for Aging Mice Became Stronger When Scientists Boosted One Protein
Spectre and Meltdown: When CPUs Leak Secrets by Guessing
🔥
Meltdown
Content type:
Blog
havenmessenger.com
·
5d
5 days ago
·
DEV
Actions for Spectre and Meltdown: When CPUs Leak Secrets by Guessing
MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
📐
Data-Oriented Design
Content type:
Academic
arxiv.org
·
5d
5 days ago
Actions for MOSAIC: A Workload-Driven Simulation and Design-Space Exploration Framework for Heterogeneous NPUs
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