Out-of-Order Execution

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Why x86 Zeroes a Register With `xor eax, eax`

 🚀Superscalar  Content type: Blog
debasishg.github.io·

The last bit – Part 3

 🔬CPU Microarchitecture
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Apple Chip Architecture from 1977 to 2026

 🚀Superscalar  Content type: News  Content type: Blog
blog.jacobstechtavern.com
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(PR) NextSilicon to Productize Arbel RISC-V Core Into 64-Core Enterprise Processor for AI and HPC

 🚀High Performance
techpowerup.com·

ARM MTE & Apple MIE: How Hardware Memory Tagging Reveals Invisible iOS Kernel Vulnerabilities

 🛡️Memory Safety  Content type: Blog
jamf.com·

x1colegal/USTP-Secure: Secure (with AEAD) version of USTP, called USTP-Secure (ustps://)

 🔬CPU Microarchitecture  Content type: Code
github.com··Hacker News

Spectre and Meltdown: When CPUs Leak Secrets by Guessing

 🔥Meltdown  Content type: Blog
havenmessenger.com··DEV

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