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RISC-V
⚙️ RISC-V
Specific
RISC-V architecture, RISC-V ISA, open source chip, RISC-V core
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Fedora 44
RISC-V
Images Released, Including New "Omni" Kernel For Broader
RISC-V
Hardware Support
📦
Chip Packaging
phoronix.com
·
3d
3 days ago
Actions for Fedora 44 RISC-V Images Released, Including New "Omni" Kernel For Broader RISC-V Hardware Support
RISC-V
Targets Data Centers, Edge AI, Space
🖥️
AI Chips
Content type:
News
eetimes.com
·
21h
21 hours ago
Actions for RISC-V Targets Data Centers, Edge AI, Space
Linux 7.2 To Enable ESWIN
SoC
Support By Default For
RISC-V
Kernel Builds
🖥️
AI Chips
lxer.com
·
1d
1 day ago
Actions for Linux 7.2 To Enable ESWIN SoC Support By Default For RISC-V Kernel Builds
"
RISC-V
Is Now"
📦
Chip Packaging
Content type:
Video
youtube.com
·
2d
2 days ago
·
Hacker News
Actions for "RISC-V Is Now"
2 to 4 cents Fortior FU75xx
dual-core
motor control MCU family combines 32-bit
RISC-V
core
with 2nd-gen Motor Engine (ME2)
core
- CNX Software
📦
Chip Packaging
Content type:
News
cnx-software.com
·
2h
2 hours ago
Actions for 2 to 4 cents Fortior FU75xx dual-core motor control MCU family combines 32-bit RISC-V core with 2nd-gen Motor Engine (ME2) core - CNX Software
RISC-V
edge box packs dual GbE, CAN, and 4G/5G support
📦
Chip Packaging
linuxgizmos.com
·
4d
4 days ago
Actions for RISC-V edge box packs dual GbE, CAN, and 4G/5G support
vpod:
RISC-V
Linux sandboxes running in WebAssembly for untrusted processes
🖥️
AI Chips
Content type:
Code
github.com
·
1d
1 day ago
·
r/rust
Actions for vpod: RISC-V Linux sandboxes running in WebAssembly for untrusted processes
SpacemiT shows off usably quick
RISC-V
mini desktop
📦
Chip Packaging
Content type:
News
theregister.com
·
2d
2 days ago
·
r/hardware
Actions for SpacemiT shows off usably quick RISC-V mini desktop
Open
Source
Hardware Certifications for May 2026
📦
Chip Packaging
makezine.com
·
3d
3 days ago
Actions for Open Source Hardware Certifications for May 2026
NextSilicon to Productize Arbel
RISC-V
Core
into
64-Core
Enterprise Processor for AI and HPC
🤖
LLM Applications
hpcwire.com
·
1d
1 day ago
·
r/hardware
Actions for NextSilicon to Productize Arbel RISC-V Core into 64-Core Enterprise Processor for AI and HPC
Vortex expands
open
RISC-V
graphics
🖥️
AI Chips
jonpeddie.com
·
1d
1 day ago
Actions for Vortex expands open RISC-V graphics
The Boot Chain of a
RISC-V
Board: From Silicon to Ubuntu 26.04
📦
Chip Packaging
Content type:
Blog
blog.ludovic.dev
·
4d
4 days ago
·
Hacker News
,
Hacker News
Actions for The Boot Chain of a RISC-V Board: From Silicon to Ubuntu 26.04
SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge
RISC-V
SoC
🔧
Semiconductors
Content type:
Academic
arxiv.org
·
2d
2 days ago
Actions for SPARX: Secure and Privacy-Aware Approximate CNN Acceleration with Edge RISC-V SoC
Openchip
taps Baya Systems data-movement platform for
RISC-V
systems
📦
Chip Packaging
siliconangle.com
·
1d
1 day ago
Actions for Openchip taps Baya Systems data-movement platform for RISC-V systems
Less-relevant results
Difference between revisions of "ELC 2026 Presentations"
🔬
ML Signal Synthesis
elinux.org
·
15h
15 hours ago
Actions for Difference between revisions of "ELC 2026 Presentations"
Docker 29 and COPY –link –chown
🔗
Datacenter Interconnects
Content type:
Blog
tunbury.org
·
5d
5 days ago
Actions for Docker 29 and COPY –link –chown
The MilkV Jupiter 2/SpacemiT K3
🏗️
AI Infrastructure
taoofmac.com
·
1d
1 day ago
·
Hacker News
,
Hacker News
Actions for The MilkV Jupiter 2/SpacemiT K3
RISC-V
Summit Europe 2026: Industry and Academia Unite in Bologna to Advance
Open
Hardware
🖥️
AI Chips
Content type:
News
eetimes.com
·
3d
3 days ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
RISC-V
CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3
📦
Chip Packaging
phoronix.com
·
2d
2 days ago
Actions for RISC-V CPU Performance Up 8x In Five Years: SiFive HiFive Unmatched To SpacemiT K3
coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification.
Tri-arch
(x86_64 / AArch64 /
RISC-V
). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.
📦
Chip Packaging
Content type:
Code
github.com
·
19h
19 hours ago
·
Hacker News
Actions for coherentforge/CambiOS: Zero-trust, capability-based Rust microkernel targeting formal verification. Tri-arch (x86_64 / AArch64 / RISC-V). Sovereign and generative: no telemetry, user owns keys and data. Early-stage — see STATUS.md. Inspired by seL4, Hubris, and Redox.
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