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CPU Architecture
💻 CPU Architecture
Instruction Sets, Pipelining, Cache, Microarchitecture
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The Tick-Tock AI Development Cycle.
⏱️
Cycle Accuracy
wilsoniumite.com
·
8h
8 hours ago
Actions for The Tick-Tock AI Development Cycle.
uiCA: Accurate Throughput
Prediction
of Basic Blocks on Recent Intel
Microarchitectures
⚙️
Virtual Machines
Content type:
Academic
arxiv.org
·
1d
1 day ago
·
Hacker News
Actions for uiCA: Accurate Throughput Prediction of Basic Blocks on Recent Intel Microarchitectures
How much do amd64
microarchitecture
levels help in Go?
⚡
RISC-V
Content type:
Blog
lemire.me
·
4d
4 days ago
·
Lobsters
,
Hacker News
,
r/golang
Actions for How much do amd64 microarchitecture levels help in Go?
Intel 8086, the First x86 chip, Enters its 50th Year in 2027
⚡
RISC-V
techpowerup.com
·
1d
1 day ago
Actions for Intel 8086, the First x86 chip, Enters its 50th Year in 2027
NVIDIA chip powers local AI workloads
⏱️
Cycle Accuracy
edn.com
·
5h
5 hours ago
Actions for NVIDIA chip powers local AI workloads
The last bit – Part 3
⚡
RISC-V
thinkingeek.com
·
4d
4 days ago
Actions for The last bit – Part 3
Apple Chip
Architecture
from 1977 to 2026
⚡
RISC-V
Content type:
News
Content type:
Blog
blog.jacobstechtavern.com
·
1d
1 day ago
Actions for Apple Chip Architecture from 1977 to 2026
New OS kernel uncovers hidden Apple M1 behavior and possible Phantom attack
💻
operating systems
techxplore.com
·
2h
2 hours ago
Actions for New OS kernel uncovers hidden Apple M1 behavior and possible Phantom attack
Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
💻
operating systems
openjdk.org
·
1d
1 day ago
·
r/java
Actions for Exploiting GPU Tensor Cores from Java using Babylon [Juan Fumero]
Founding Engineer - FPGA, RTL, & ASIC
Architect
at Zettascale
🔧
Kernel Development
ycombinator.com
·
6d
6 days ago
·
Hacker News
Actions for Founding Engineer - FPGA, RTL, & ASIC Architect at Zettascale
Why x86 Zeroes a
Register
With `xor eax, eax`
⚡
RISC-V
Content type:
Blog
debasishg.github.io
·
2d
2 days ago
Actions for Why x86 Zeroes a Register With `xor eax, eax`
RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
⚡
RISC-V
Content type:
News
eetimes.com
·
2d
2 days ago
Actions for RISC-V Summit Europe 2026: Industry and Academia Unite in Bologna to Advance Open Hardware
Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
💻
operating systems
Content type:
Blog
elastic.co
·
5d
5 days ago
Actions for Elasticsearch simdvec deep-dive: Walking the memory tightrope to 2x better vector throughput
Nvidia RTX Spark Gaming: GB10 ARM Silicon and Windows on ARM Laptop Demo
📦
QEMU
armdevices.net
·
6d
6 days ago
Actions for Nvidia RTX Spark Gaming: GB10 ARM Silicon and Windows on ARM Laptop Demo
Intel introduced ‘the first processor in the x86 series and the first 8086 microprocessor’ on this day in 1978 —
CPU
was
designed
as a temporary substitute for the delayed iAPX 432 project
🎛️
Microcontrollers
Content type:
News
tomshardware.com
·
2d
2 days ago
Actions for Intel introduced ‘the first processor in the x86 series and the first 8086 microprocessor’ on this day in 1978 — CPU was designed as a temporary substitute for the delayed iAPX 432 project
AMD says that no decision has been made about bringing FSR 4.1 to RDNA 3.5 GPUs, which seems to contradict AMD also saying that it has no current plans to do so...
🔐
Hardware Security
Content type:
News
pcgamer.com
·
5d
5 days ago
Actions for AMD says that no decision has been made about bringing FSR 4.1 to RDNA 3.5 GPUs, which seems to contradict AMD also saying that it has no current plans to do so...
Infinix GT 50 Pro review
🎛️
Microcontrollers
gsmarena.com
·
2d
2 days ago
Actions for Infinix GT 50 Pro review
The copy_if Speedup That Wasn't About copy_if, Or AVX-512
⚙️
Virtual Machines
hftuniversity.com
·
6d
6 days ago
·
Substack
Actions for The copy_if Speedup That Wasn't About copy_if, Or AVX-512
Sequential hardness of a MUL-XOR-shift permutation: open questions
⚙️
Virtual Machines
Content type:
Code
github.com
·
1d
1 day ago
·
r/crypto
Actions for Sequential hardness of a MUL-XOR-shift permutation: open questions
Fractal OS Lets Security Researchers See What Their CPUs Really Do
💻
operating systems
Content type:
News
spectrum.ieee.org
·
1d
1 day ago
Actions for Fractal OS Lets Security Researchers See What Their CPUs Really Do
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