Huawei Just Rewrote the Rules of Chip Design With Its New Tau Scaling Law and the Chinese EDA Industry Has Lined Up Behind Empyrean and Peking University to Cat... (opens in new tab)

Huawei's announced Tau Scaling Law and LogicFolding 3D-integrated-circuit architecture set out a path to 1.4 nanometre-equivalent chip performance by 2031 without lithography below 7 nanometres, Empyrean Technology's Argus 3D physical-verification platform and the Peking University true-3D EDA-tool prototype have lined up behind Huawei's framework, and the cumulative Chinese semiconductor-design-software ecosystem is now positioning to compete with Synopsys, Cadence and Siemens EDA at the arc...