For decades, the progress of electronics has followed a simple rule: smaller is better. Since the 1960s, each new generation of chips has packed more transistors into less space, fulfilling the famous Moore’s Law. Formulated by Intel co-founder Gordon Moore in 1965, this law predicted that the number of transistors in an integrated circuit approximately doubles each year. But this race to the minuscule is reaching its physical limits. Now, an international team of scientists is proposing a solution as obvious as it is revolutionary: if we can’t keep reducing the size of chips, let’s build them up.

Xiaohang Li, a researcher at King Abdullah University of Science and Technology (KAUST) in Saudi Arabia, and his team have designed a chip with 41 vertical layers of semiconductors and insulating materials, approximately ten times higher than any previously manufactured chip. The work, recently published in the journal Nature Electronics, not only represents a technical milestone but also opens the door to a new generation of flexible, efficient, and sustainable electronic devices.

“Having six or more layers of transistors stacked vertically allows us to increase circuit density without making the devices smaller laterally,” Li explains. “With six layers, we can integrate 600% more logic functions in the same area than with a single layer, achieving higher performance and lower power consumption.”

Moore’s Law began to lose its validity around 2010, when chip manufacturers encountered the laws of physics. Today’s transistors are only a few nanometers wide, so small that quantum effects begin to interfere with their operation. “Moore’s Law is reaching its physical limits in traditional silicon microelectronics, but innovation continues in new directions. Instead of continuing to shrink transistors, we are exploring new materials, new architectures, and new possibilities, such as stacking,” says Li.

Transistor skyscrapers

To understand the technical challenge his team faced, Li uses an architectural metaphor: “Think of each layer of transistors as the floor of a skyscraper. If one floor is uneven, the whole building becomes unstable.” The key to the experiment’s success was mastering what they call “interface roughness”: any tiny imperfection between layers can disrupt the flow of electrons and drastically reduce the chip’s performance.

The fundamental breakthrough was developing entirely new manufacturing strategies. A crucial point was ensuring that all layers were deposited at or near room temperature, thus protecting the layers already constructed below. This low-temperature manufacturing is not merely a technical detail. “Most flexible or organic materials cannot withstand high temperatures,” explains Li. “Traditional semiconductor processes often exceed 400°C, which would melt or deform these materials,” he adds. Keeping the entire process close to room temperature allows the use of plastic or polymer substrates, opening the door to the flexible electronics of the future.

To demonstrate the viability of their design, the team made 600 copies of the chip, all with similar performance. The researchers used these stacked chips to implement basic operations, achieving performance comparable to traditional non-stacked chips but with significantly lower power consumption: just 0.47 microwatts, compared to the typical 210 microwatts of state-of-the-art devices.

First applications

Where will we first see this technology? Li is optimistic but realistic: “The first applications will likely be wearable health sensors, smart tags, and flexible displays, where low power consumption and mechanical flexibility are crucial.” In the longer term, the team envisions large-area computing surfaces—essentially “electronic skins” that can sense, process, and communicate through objects or entire structures. While these new chips probably won’t power supercomputers, their use in devices like household appliances could significantly reduce the electronics industry’s carbon footprint.

“The circuits we develop are designed for these systems, where mechanical flexibility, low cost and scalability matter more than extreme speed,” Li explains. The researcher believes his research opens a new door in computing: “It shows that performance scaling can continue, not only by making devices smaller, but also by integrating them more intelligently and efficiently in three dimensions.”

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