When engineers start designing a new semiconductor technology and fabrication process, they set targets to define what they are trying to achieve to meet the market demands and beat competitive offerings. Traditionally, they have used the metrics of power, performance, and area (PPA). This post examines how additional design targets are mandated by today’s deep submicron nodes and how developers can optimize for all targets.

Bringing up new technologies

There are two major phases in the development of a new chip technology. The second phase entails prototyping the manufacturing flow, fabricating test chips, and creating and refining process development kits (PDKs). As the process moves into full production, the integration and process teams work on optimizing the manufacturing technology, selecting fab tools, and upgrading these tools as needed.

The number of test chips during the second phase must be minimized since manufacturing using advanced nodes is expensive, with long fabrication times. This is possible by diligent effort during the first phase of technology development to design and optimize individual devices, extract compact models, define layout rules, and optimize the process flow. Traditionally, the PPA metrics have been used to measure the success of this effort.

Circuit simulation and technology computer-aided design (TCAD) simulation are the core of this first phase. Simulation runs are used to build and validate process assumptions, and iterate process and design rules to meet PPA targets, prior to fabricating expensive test wafers. Design technology co-optimization (DTCO) enables optimizing the design and technology process flow together. New materials and new transistor architectures can be efficiently tested, optimized, and evaluated.

Going beyond PPA

In advanced nodes, PPA targets are insufficient to capture the full range of design goals. For example, wafer fabrication cost is critical. The fabrication process and fabrication facility must both be taken into account. The same process in two different fabs or two different processes in a single fab may have dramatically different costs. The wafer fab must be defined in detail and the process must be defined at a step-by-step level, with appropriate calculations performed for each step.

Another key metric is the cycle time to fabricate a wafer. The ideal cycle time occurs only if every tool in the fab is ready to immediately process the wafer when it arrives at each step. In practice, wafers frequently encounter wait times due to tools that are down or busy, leading to an actual cycle time. Xideal, the actual cycle time divided by the ideal cycle time, depends upon the fab configuration, how loaded the fab is, operational decisions, and random events.

Finally, environmental impact as measured by carbon footprint is increasingly important. This can be estimated by determining the materials and material quantities used in the process flow and then applying utilization, abatement, and global warming factors. The result is that new technology development targets are evolving from PPA to PPACtE, with cost (C), cycle time (t), and environmental (E) in the form of carbon equivalents included.

PPA optimization solution

The Synopsys DTCO Solution helps semiconductor fabs reduce cost and accelerate time to market (TTM) in advanced process development. Technology development teams generate new patterning techniques, evaluate and optimize new transistor architectures, and extract compact models. They then use derived design rules to design and characterize a standard cell library and carry out block-level PPA evaluations.

Synopsys Sentaurus Process Explorer is a process analysis and visualization tool within the Sentaurus TCAD suite. Its DTCO capabilities enable engineers and researchers to interactively explore, debug, and optimize simulation results, bridging the gap between process integration and device performance. This helps process developers collaborate with design teams by providing clear visualizations and measurements that impact standard cell design and PDK development.

Process Explorer supports process integration debugging for quick identification and resolution of bottlenecks in process integration. As the process matures, it supports yield and reliability improvement by detecting and analyzing structural anomalies that could compromise yield, and correlating physical structures with reliability concerns such as stress-induced voiding and critical dimension control.

Extending the solution to PPACtE

The Synopsys DTCO Solution enables iterative simulation of process flows and device structures to meet PPA goals. However, it does not natively simulate or optimize for cost, cycle time, or environment/carbon footprint. TechInsights has developed Cost Explorer, a plug-in for Process Explorer that adds CtE to provide a complete PPACtE solution. Adding the results of Cost Explorer analysis into the Process Explorer evaluation metrics enables full PPACtE optimization.

Before a process is passed to Cost Explorer from Process Explorer, engineers must develop a realistic process flow description in Process Explorer and define the fab parameters. These include:

• Fab capacity
• Date the fab was constructed
• Product type (logic, DRAM, NAND, etc.)
• Process node
• Lot size
• Fab utilization (percentage)

The process flow is defined step by step, selecting a piece of equipment to perform the step and parameterizing the equipment usage. Parameters include equipment type, utilization, metrics, configuration, throughput, material usage, electricity cost, purchase cost, cleanroom footprint, and fab cost.

Cost Explorer uses the detailed definitions of the equipment used for each step, with throughput and materials requirements, to perform detailed calculations. Direct labor, depreciation, equipment maintenance, indirect labor, facilities, and materials costs are all estimated. Other calculations include cost per step, equipment required for the fab, labor costs, facilities requirements, detailed material usage and cost, ideal cycle time, and carbon footprint, plus annual costs for labor, utilities, reticles, and materials.

Conclusion

The combination of Cost Explorer, Process Explorer, and DTCO Solution enables process optimization for PPACtE in a TCAD environment before committing to running test wafers. This new capability can provide more efficient development at lower cost and highly optimized process technologies for long-term manufacturing cost, cycle time, and carbon savings.

To find out more about this integration, including a real-world case study from Tokyo Electron, a detailed white paper is available from TechInsights.