Cadence’s Sandip Sadadiya shows what’s new in the AMBA AXI Issue L protocol update, which introduces a new credit-based transport mechanism that replaces the traditional VALID/READY handshake, along with improved flow control mechanisms.

Siemens’ Farhad Ahmed highlights the growing need to do clock domain crossing (CDC) and reset domain crossing (RDC) analysis in a hierarchical way and introduces an effort to create a standard format for hierarchical data models so they can be consumed by any EDA tool irrespective of the source of the generated model.

Synopsys’ Varun Shah and Xingang Zhao suggest adopting a hybrid cloud approach that enables EDA workloads to burst from on-prem systems to the cloud during peak demand, providing agility, data continuity, and cost efficiency without overbuilding infrastructure that remains underutilized during quieter phases of the design cycle.

Arm’s Marc Meunier highlights how Fujitsu implemented confidential computing on its FUJITSU-MONAKA HPC CPU by using hardware-isolated execution environments that make the contents of sensitive workloads inaccessible to the host OS or hypervisor, a hierarchical memory architecture with workload management across chiplets, and software stack integration.

Keysight’s Scott Register considers medical device cybersecurity as threats to the healthcare sector have become more frequent and more severe, and how the FDA is reacting with new requirements around cybersecurity testing and reporting.

Ansys’ Laura Carter highlights model-based systems engineering (MBSE) as a critical methodology in managing high levels of automotive complexity, enabling engineers to work collaboratively to navigate requirements and validate next-generation vehicle designs early, with greater efficiency.

In a blog for SEMI, PDF Solutions’ Alan Weber introduces a common security assessment process for device makers, equipment suppliers, software suppliers, and other members of the global manufacturing value chain to help streamline compliance, evaluate cyber readiness, and reduce supply chain risk.

Plus, check out the blogs featured in the latest Automotive, Security & Emerging Technologies, Test, Measurement & Analytics, and Low Power-High Performance newsletters:

Tech strategy advisor Geoff Tate digs into data center LLMs and the need for more petaflops, memory capacity, and bandwidth.

Rambus’ Raj Uppala explains how continuous monitoring for abnormal environmental or electrical conditions can help detect attacks.

Cadence’s Sriram Kalluri argues that despite their specialization, NPUs are not a silver bullet for the entire AI pipeline.

Synaptics’ Nebu Philips points to a new class of MPUs and MCUs to address IoT fragmentation.

Siemens’ Matthew Hogan presents a shift-left imperative for preventing failures in automotive electronics.

Synopsys’ Vincent van der Leest and Geert-Jan Schrijen propose a secure, cost-effective, and scalable solution for cryptographic key generation and storage.

Keysight’s Marc Witteman breaks down how vendors are obligated to address security vulnerabilities throughout the product’s lifecycle.

Infineon’s Joyce Chabert digs into a dedicated safety MCU that provides robust hardware and software separation, real-time performance, and scalability.

Imagination’s Patrik Masson details a GPU driver update with new cooperative matrix, pipeline compilation, and memory management improvements.

Onto Innovation’s Damon Tsai, Woo Young Han, and Tim Kryman dig into how bump technologies are being pushed beyond what was thought to be their physical and performance limits.

Synopsys’ Nozar Nozarian looks at sustained structural test coverage and diagnostic depth throughout the operational life of a product.

PDF Solutions’ John Kibarian contends that the convergence of AI, analytics, and data sharing is the most significant operational evolution since the foundry model.

Modus Test’s Jesse Ko describes how the gap between lab measurements and real-world applications can lead to sub-optimal socket selection and hidden quality risks.

proteanTecs’ Alex Burlak examines the diverse approaches and innovative solutions shaping the future of AI hardware.

Siemens’ Vidya Neerkundar discusses the transformation of traditional serial IJTAG operations into high-speed parallel processes.

Advantest’s Arik Peltz argues that as the scope of potential vulnerabilities continues to grow, perimeter defense alone is not enough.

Fraunhofer EAS’ Andy Heinig explains a new design paradigm that combines mechanical, electrical, thermal, and optical aspects in an integrated system concept.

Arm’s Marc Meunier and AMI’s Srini Narayana argue that firmware must dynamically orchestrate each chiplet’s power domain, boot sequence, security enclave, and thermal profile.

Synopsys’ Abhinav Kothiala talks about maintaining signal integrity and minimizing bit error rates under high-speed conditions in extended reach cables.

Rambus’ Nidish Kamath points out that as inference proliferates to edge servers and endpoints, memory solutions must balance performance, cost, and power efficiency.

Quadric’s Steve Roddy suggests a different way to evaluate the ease of porting an AI model to certain hardware.

Ansys’ Susan Coleman and Emily Gerken dig into combining silicon photonics and analog mixed-signal components in optical transceiver chiplets.