Scaling the back end of line (BEOL) in advanced semiconductor logic devices is a major challenge. Metal lines and via filling in BEOL have historically used copper (Cu) as the electrical conductor. But as device dimensions shrink, Cu use has become problematic. The small critical dimensions (CD) of the Cu metal lines and vias in the latest BEOL structures have created an increase in resistance, impacting device performance.

• This increase in resistance is from increased Cu resistivity at a small Cu volume.1
• The Cu dual damascene (DD) process is limited in scaling below certain barrier metal thicknesses due to reliability issues.2
• Stress-induced voids (SIVs) can also lead to increased interconnect resistance.3

Hybrid metallization

Hybrid metallization is a new technique that uses bottom-up deposition to prefill a via with barrierless metals. Barrierless metals are metal interconnects that do not require a separate diffusion barrier layer between the metal and the surrounding dielectric or semiconductor materials. This hybrid metallization technique is followed by a conventional Cu DD process.

This technique can be initially adopted in bottom via contact areas, where via resistance is rapidly increasing due to smaller device dimensions, and could be used to replace all Cu lines and vias with alternative barrierless metals.

We conducted a pathfinding study that compared a conventional Cu DD scheme against a hybrid metallization scheme using molybdenum (Mo). Our studies were conducted using SEMulator3D, which was also used to develop process specifications for optimal via metal line profiles.

Via/line resistance

Figure 1 displays a graph of via/line resistance for various metal via schemes. In this example, the total resistance benefit of a Mo hybrid scheme is about 55% when compared to a conventional Cu DD process scheme.

Fig. 1: M1 to M3 resistance (via/line) by various metal/via schemes.

Selective barrier deposition (SBD) techniques can also be introduced to avoid depositing barrier metal on top of the vias. Total resistance is reduced by an additional 15% with SBD (right data set in Figure 1), with via resistance almost the same with or without SBD.

In Figure 2, total current density using both Mo vias and SBD techniques is much higher, as expected, since they exhibit lower resistance values.

Fig. 2: Current density of various metal/via schemes. Red and green areas indicate higher current density.

The current density of V1 Mo and V1/V2 Mo are much higher than when a Cu DD scheme is used, since additional current can flow when a barrier metal is not used.

Optimizing metallization

We studied stress distribution using the conventional Cu DD and Mo hybrid schemes. There is a greater stress gap in the Z direction between M1 and V1 using a Cu DD scheme than if a Mo via scheme were used. This is most evident between via V1 and the barrier metal layer (see the red area in Figure 3[a]).

The maximum stress gap between V1 and M1/M2 is higher for Cu. Stress-induced voids can be generated at metal/barrier interfaces or metal/dielectric interfaces due to stress gradients4. There is a higher probability of voids at the bottom of a via formed using Cu DD than one built using Mo hybrid metallization.

Fig. 3(a): Stress distribution of Cu DD and Mo hybrid metallization.

Fig. 3(b): Via resistance and hydrostatic stress as function of Mo height.

Resistance and mechanical stress within a Mo prefill profile was analyzed in an M1 to M3 BEOL interconnect scheme. The hydrostatic stress gradient between the Mo via and M1, and between the Mo via and M2, increases with increasing Mo height. Total resistance of M1 to M3 decreases as the Mo height increases.

Since the resistance slope saturates when the Mo height exceeds 25 nm, and the M1 stress gradient increases between the Cu/barrier metal and the Mo with increasing Mo height, the optimal Mo height might be the amount required to fill up to the via height and satisfy resistance and stress targets.

Via stress can also be controlled through use of materials with varying properties, such as intrinsic stress and process temperature. Figure 4(a) displays Mo via stress as a function of Mo intrinsic stress. Via hydrostatic stress can be reduced by choosing a material with the compressive intrinsic stress of Mo.

As seen in Figure 4(b), the via hydrostatic stress decreases with increasing temperature; however, M2 stress rapidly increases. Since stress-induced voids can be caused by a higher stress gradient, a smaller stress value difference between the via and M2 is preferred in our example by keeping the temperature at about 400°C. M2 stress can also change from tensile to compressive at higher temperatures.

Fig. 4(a): Via hydrostatic stress with intrinsic stress.

Fig. 4(b): Via hydrostatic stress and its distribution as function of process temperature.

To identify an optimal via metal line profile using hybrid metallization, we performed a uniform Monte-Carlo simulation with 400 experimental runs in SEMulator3D. We identified four parameter candidates that could help achieve this profile by using a linear regression analysis. As shown in Figure 5(a), as the via top critical dimension (CD) and bottom CD increase, via stress and total resistance decrease.

Fig. 5(a): Sensitivity analysis of different process parameters and their impact on hydrostatic stress, M1-M3 resistance, and M1-M2 capacitance. Parameters analyzed include via top and bottom CD, via height, and M2, with metrology targets shown for capacitance.

Conversely, as via height increases, via stress and total resistance also increase. Capacitance between M1 and M2 increases as via height (the distance between M1 and M2) decreases and via CD increases. Thus, there is a limit to reducing via height due to leakage current in the high dielectric field between M1 and M2. The leakage current can lead to intrinsic unreliability such as time dependent dielectric breakdown (TDDB).

We developed an optimal via profile using the sensitivity analysis (Figure 5[b]).

Fig. 5(b): Via profile optimization with stress distribution.

Conclusion

In this study, we demonstrated a methodology to provide pathfinding guidance for hybrid metallization using Mo. Using virtual fabrication and a virtual Design of Experiment (DOE), we were able to identify the optimal Mo via profile that will minimize mechanical stress that contributes to voids and were also able to minimize RC parasitic effects. Using this technique, we can predict the impact of process changes using new process schemes like hybrid metallization, without the time and cost of extensive wafer-based experimentation.

References

1. Founta Valeria, Witters Thomas, Mertens Sofie, Vanstreels Kris, Meersschaut Johan, Van Marcke Patricia, Korytov Maxim, Franquet Alexis, Wilson Chris, Tokei Zsolt, Van Elshocht Sven, and Adelmann Christoph. “Properties of Ultrathin Molybdenum Films for Interconnect Applications,” Materialia 2022, Vol. 24, p. 101511.
2. Z. Tőkei, I. Ciofi, P. Roussel, P. Debacker, P. Raghavan, M.H. van der Veen, N. Jourdan, C.J. Wilson, V. Vega Gonzalez, C. Adelmann, L. Wen, K. Croes, O. Varela Pedreira, K. Moors, M. Krishtab, S. Armini, and J. Bömmels. “On-Chip Interconnect Trends, Challenges, and Solutions: How to Keep RC and Reliability Under Control,” 2016 IEEE Symp. VLSI Technol., pp. 182–183.
3. Gayle Murdoch, Zsolt Tokei, Sara Paolillo, Olalla Varela Pedreira, Kris Vanstreels, and Christopher J. Wilson. “Semidamascene Interconnects for 2nm Node and Beyond,” IEEE IITC 2020, pp.4-6.
4. Charlie Jun Zhai, H. Walter Yao, Amit P. Marathe, Paul R. Besser, and Richard C. Blish. “Simulation and Experiments of Stress Migration for Cu/Low-k BEoL,” IEEE Trans. Device Mater. Reliab. 2004, Vol. 4, pp. 523-529.

Taeyeon Oh

(all posts) Taeyeon (TY) Oh, Ph.D. is a staff semiconductor process and integration engineer with Korea Semiverse Solutions R&D at Lam Research. In this position, he is responsible for semiconductor process integration & device simulation activities for DRAM, NAND and other device technologies. Prior to working at Coventor, Oh worked as a DRAM Senior Engineer (Manager) at Samsung Electronics, where he developed advanced DRAM manufacturing processes, performed failure analysis and assisted in yield improvement activities. Dr. Oh received his Ph.D. in Electrical and Electronic Engineering from Korea University, where he studied the design and fabrication of flexible electronic devices.