Key Takeaways

  • Over 50% of IC/ASIC project time is spent on verification, requiring as many verification engineers as design engineers, which highlights the importance of improving verification processes.
  • The acceptance rate for generated RTL via GenAI is around 25%, indicating that while progress is being made, generated logic often requires manual adjustments and is not yet fully reliable.
  • Debugging represents a significant opportunity for improvement in verification, accounting for 47% of verification effort, with potential gains from agentic approaches to triage and root-cause analysis.

I should admit up front that I don’t have a scientific answer to this comparison, but I do have a reasonably informed gut feel, at least for the near-term. The reason I ask the question is…

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